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What Happens When Routing Over Splits In Power Planes — Transcript

by Altium Academy · 2,648 words · 374 segments · language en · Watch on YouTube

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0:00Hello everybody welcome back to altm
0:02Academy I'm your host Zack Peterson and
0:04today we're going to be looking at
0:07routing over splits in power planes
0:10should you do it we're going to answer
0:12that question in this video now Bert
0:14simonovich recently put out a paper and
0:16Signal Integrity Journal that examined
0:18this and I wanted to examine the same
0:20thing in Al team designer and symor what
0:23I'm going to do in this video is show
0:24you how to set up a test board properly
0:26in order to do a simulation of this and
0:29then we'll look at what happens when we
0:30actually route over a split between two
0:33large power rails with strip line
0:34routing make sure to hop into Alam
0:36designer and follow along and let's get
0:41[Music]
0:49started now the situation that we want
0:51to look at in this video involves strip
0:53line routing and it typically arises
0:55when you have six layer boards typically
0:57when you have a six layer board that's
0:59designed for high speed you'll have
1:01signal on the top layer and then you'll
1:03have symmetric signal on the bottom
1:06layer then on layers two and layer five
1:11you will typically have ground and then
1:14another layer with ground now one of the
1:16reasons that you might use a six layer
1:18board is because one of your internal
1:20layers can also be Sig so we have some
1:23signal routing in this layer but then
1:25you can typically have a power layer
1:28here as well now one thing that often
1:30happens in these situations with power
1:32layers is you may have two different
1:34rails one routed with V1 and then the
1:38other routed with voltage V2 now as
1:40you're routing your signal layer around
1:42in this internal part of the stackup you
1:44may end up routing over one of these
1:47splits in this power layer does this
1:49split actually matter well that's the
1:51situation that we want to look at in
1:53this video and we're going to run some
1:55simulations to determine whether or not
1:57it does actually matter I think the
1:59intuition here is that because you have
2:01a ground plane above this signal layer
2:04then the signal layer is still going to
2:06be strongly coupled to the ground plane
2:08and you may expect that the impedance
2:10deviation here in this region where you
2:14have the split between your power rails
2:16might be negligible and as a result you
2:18can probably ignore this well I think
2:21this is one of those things that require
2:22some context at certain frequencies it
2:25may not matter and at other frequencies
2:27it might actually matter so this is one
2:29of those things that you really should
2:30simulate the reason is that because here
2:33in this region where you have the solid
2:35power plane you have the impedance
2:37determined by Layer Two and layer four
2:41and so you would then put Layer Two and
2:42layer four as your references into the
2:44impedance calculator such as if you're
2:46using the layer stack manager and altham
2:48designer however in this region your
2:50reference is no longer layer four your
2:52reference is actually Layer Two in this
2:54region and then layer five down here so
2:57you have slightly more distance from
2:59from the signal to the bottom uh
3:02reference layer which could then create
3:03your impedance deviation will this
3:05actually matter well it depends on the
3:07input impedance looking over this
3:10direction through the signal layer now
3:12this is something that we can actually
3:14simulate in an electromagnetic simulator
3:16and what we want to do is look at the S
3:18parameters so since we're dealing with
3:20an input impedance deviation right here
3:22in this region we would then want to
3:24calculate our S11 value for the traces
3:28that are being routed over this region
3:30now another question that you might ask
3:32is is there going to be a difference for
3:34single-ended signals versus differential
3:36signals so for single-ended signals the
3:39only reference you have are these plain
3:41layers above and below the signal layer
3:44but if you have a differential signal
3:46the differential signal can provide the
3:47return path and it functions as the
3:49reference for one of the other traces so
3:52is that going to produce a difference
3:54we're going to look at that situation as
3:55well we'll look at single-ended s
3:58parameters and we'll look at
4:01differential as parameters when we do
4:03our simulation now let's jump into alt
4:05team designer we'll take a look at how
4:07to set up a test board for this type of
4:09situation and then we'll throw that into
4:11a simulator and we'll get our s
4:12parameters and we'll see what the
4:14difference is between routing over solid
4:16power versus routing over split power so
4:19now I'm inside of Altium designer and
4:20what I want to do is show you how to set
4:22up a test board in order to accurately
4:24perform simulations for this power plane
4:26split so here inside of Altium designer
4:28what I've done is just created kind of a
4:30simple model where I have two different
4:31sizes of gaps for our power plane split
4:34and then I've created an identical set
4:36of interconnects over a solid uh ground
4:39and power plane now if we look at the
4:41stackup you can see here where our power
4:43ground and Signal planes are located
4:45here on the top and bottom layers we
4:47have a uniform ground here Layer Two is
4:50our power layer that's where our split
4:51is going to be and then Layer Three is
4:53our signal layer so that's where our
4:55signals are being routed in this example
4:58simulation model that I've created ated
5:00I've placed two different size gaps so
5:02here I have a 400 mil Gap and here I
5:03have a 200 mil Gap and then if you look
5:06at the schematics here I've defined
5:08single-ended and differential traces
5:10that we can use to simulate what happens
5:12for our different types of signals when
5:13they route over these gaps now on each
5:15end of these nets what I've done is I've
5:17created these dummy components and these
5:19dummy components are basically just a
5:20pad that's going to make it very easy to
5:22assign a port on each end of these
5:25interconnects when we then import this
5:27into the simulation tool now one thing
5:28I'd like to do uh before we jump into
5:30simulation is to just discuss these via
5:32transitions now you can see here I've
5:34placed some stitching vas around these
5:36signal Vias and then you can see that
5:38there's kind of a default anti-ad around
5:40these signal Vias depending on the
5:42frequency range that you're working in
5:44you would actually want to design these
5:46vas so that they have a 50 ohm impedance
5:49specifically in the frequency range that
5:51you care about for this demo we're not
5:54going to worry about that because that's
5:55a whole another level of complexity but
5:57in general if you were going to create a
5:59Sim simulation model and whether you
6:00were going to use Anis or use symor or
6:03some other simulator you would want to
6:05make sure that that via transition
6:06provides correct matching if you can't
6:08do that you would then need to relocate
6:11the pad for this port to an internal
6:13layer and eliminate those Vias now the
6:16other thing that you might want to do
6:17again depending on the frequency range
6:19you're working in is move the location
6:21of this split closer to your input Port
6:24so for lower frequencies you can have
6:26this somewhat farther away whereas at
6:28higher frequencies would want to move
6:30this Gap closer to the input so to do
6:34that is pretty simple you're of course
6:35just dragging the Gap here from these
6:37polygons closer to your input side then
6:40you would just size it so that you have
6:41the correct gap size here I'm going to
6:43leave it here just in the middle and
6:44we're going to see what happens when we
6:46simulate the S parameters we're going to
6:48look at how the different size gaps
6:50influence our s parameters in different
6:53frequency ranges for this set of
6:54simulations we're going to use symor to
6:56get your board into symor you would just
6:58do an obb b++ export and then you can
7:01reimport the board back into symor and
7:03start selecting the Nets that you want
7:05to simulate so now I've brought the
7:06board up in symor and now I can start
7:08selecting the ports that I want to
7:10simulate here when I'm in symor what I
7:12can immediately do is just run an ERC
7:15and I can see what the expected
7:16impedance deviation is along this
7:19section of interconnect so you can see
7:20here for the differential pair with the
7:23200 mil Gap that we have a 6 ohm
7:25deviation in the differential impedance
7:28here if we go back to the single-ended
7:31port and I run the same you can see that
7:33I get an 8 ohm deviation so it's
7:35actually much more significant when you
7:37have the single-ended signal versus the
7:40differential signal for the single-ended
7:42signal it's a almost 20% deviation in
7:45the impedance whereas it's only a 6%
7:47impedance for the differential pair so
7:49that should underscore the importance of
7:51having differential Pairs and sometimes
7:54having them spaced closer together when
7:56they're closer together and you route
7:58over this kind of split split you're
7:59going to have a smaller deviation in the
8:01differential impedance that's because
8:03one Trace always references the other
8:05Trace next let's start selecting our
8:07ports here and then we can set up a
8:09quick s parameter simulation so here I'm
8:10going to select our 200 mil Gap our 400
8:13mil Gap and then our uniform plane and
8:16I'm going to run a fast SI simulation to
8:18get the S parameters so now we have our
8:20return loss data pulled up and the
8:22return loss data pretty clearly shows
8:24what happens when you have that split in
8:26the plane especially when it's a
8:27reasonably large split here when we look
8:30at really low frequencies we see that
8:32all the s parameters pretty much overlap
8:34with each other and this is when we're
8:36sub 100 uh megahertz or right around 100
8:39megahertz once we start to get into the
8:41gigahertz range we really start to see
8:43the deviation in the S parameters really
8:45quickly here the blue curve is for s33
8:49and that's for this middle Trace right
8:51here so that's where we have the uniform
8:53plane then here the red is S11 so that
8:56is for our top left corner here that's
8:58where we have we have our smaller Gap
9:00and then here the brown or the orange
9:02curve that is our Trace down here in the
9:05lower right which is our 400 mil Gap so
9:08this is where we start to see a pretty
9:09big deviation in the S parameters in the
9:11one to about 7 or 8 gigahertz range and
9:16you can see here that we do get pretty
9:17high return loss compared to the trace
9:21over uniform planes however is this too
9:24much reflection well as we can pretty
9:26clearly see in this case the return loss
9:29does get pretty high but it doesn't jump
9:31up above -10 DB in a lot of cases this
9:34would probably still be acceptable even
9:36if we're routing over these large gaps
9:39now once you get around 10 GHz in higher
9:41frequencies we see that the S parameters
9:44all start to overlap each other a little
9:46bit so this is because the dominant
9:48return loss mechanism switches from the
9:51Gap in the power plane to the loss or
9:54the impedance deviation that's created
9:56by the loss in these interconnects now
9:58remember remember an Al team designer
10:00it's determining a lossless impedance
10:02but the real interconnects have
10:04dialectric loss tangent as well as Skin
10:06effect that create deviations in the
10:08impedance and that's what's creating
10:10these Reflections at much higher
10:11frequencies so our conclusion is this at
10:13really low frequencies sub one gigahertz
10:16you're really not going to notice a
10:17difference once you get into the low
10:19gigahertz range you do start to see a
10:21large difference however with the small
10:23spacing that we have between ground and
10:25Signal it doesn't create so much loss
10:28that the interconnect may not still be
10:29usable once we get to really high
10:31frequencies the split in the plane
10:34becomes less important and you have
10:35other loss mechanisms that are creating
10:37the impedance deviation that you see in
10:40these s parameter plots now let's take a
10:42look at the differential s parameters
10:44for all of these differential pairs in
10:45this test board we have all of the
10:47differential s parameters prepared now
10:49what you can see here is that all of the
10:52differential s parameters are pretty
10:54similar we have the same ordering here
10:56for these curves by color the gapless
10:58and the small small Gap and the large
11:00gap are all really similar all the way
11:02up to really high frequencies this can
11:05be explained in a couple of ways first
11:07of all as we saw earlier the impedance
11:09deviation when routing over that split
11:11in the power plane was smaller for the
11:13differential pairs remember it was only
11:146% whereas for the single-ended traces
11:17it was almost 20% next we have the same
11:19change in the dominance of the return
11:22loss from low to high frequencies as we
11:25had in the single-ended case so just
11:27because we're in differential pairs
11:29doesn't mean that the Lost tangent and
11:31the skin effect go away they also will
11:33dominate and create an impedance
11:35deviation scene looking into the
11:37interconnect and so that's what's
11:39creating this big deviation at higher
11:41frequencies and then creating this
11:42higher return loss Rising just above1 D
11:45so this channel would still be
11:47appropriate all the way up to about 20
11:49GHz but to really perfect this we would
11:52want to do what I stated earlier both
11:53for the single-ended transition and the
11:56differential transition and that would
11:58be to optim ize these Vias so that we
12:01get a really flat near 50 ohm single
12:04eded impedance or 100 ohm differential
12:06impedance within the bandwidth that we
12:08care about that's going to help
12:09eliminate some of this discrepancy and
12:11then it's going to give us a little bit
12:12more accurate view into what's happening
12:15with our system now as I've shown in
12:16some other videos we really don't care
12:18about the Via impedance until we get
12:20above a couple of gigahertz so if we
12:23were only looking from for example uh up
12:26to 2.5 GHz here we could get a really
12:28clear view of what's going on in both
12:30sets of Curves here if we just zoom in
12:33to the 2.5 GHz range for our
12:36single-ended uh traces we see here the
12:38really big impedance deviation that we
12:40get when there's Gap versus no Gap and
12:42it's a it's a little over 20 DB for the
12:45differential pairs we have a much
12:46smaller deviation between the return
12:48loss curves so it's a little bit more
12:51difficult to conclude that the split in
12:53the power layer is the sole cause of all
12:55of this Behavior to really nail that
12:57down we would definitely want to
12:59optimize those vas or we could bypass
13:01the vas completely and just move those
13:03pads into the inner layer and then
13:06assign our Port directly to those pads
13:08on the inner layer make sure to take a
13:09look at the blog that's Linked In the
13:11description to learn more about this and
13:12I'll discuss this further in that blog
13:14thanks for watching everybody make sure
13:15to hit that subscribe button hit that
13:17like button leave your comments and
13:18questions in the comment section and of
13:20course don't forget to call your
13:21fabricator folks we'll see you next
13:23[Music]
13:24[Applause]
13:27time

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