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W3 RISC V ISA I Part2 EN — Transcript

by Hasan Erdem Yantır · 5,568 words · 1,011 segments · language en · Watch on YouTube

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0:02So,
0:04yeah, in here while when I call a
0:06function, I am registering the return
0:08address, and after this function runs,
0:12there is a return instructions. Always
0:14functions has return instructions, and
0:17this return instructions jumps to the
0:20location that I saved before, before
0:22calling this function. While or while
0:25while calling this function.
0:30We will see more detailed examples.
0:33Uh these are the extensions for INM. We
0:37We saw INM extensions. Uh there are
0:40floating point extensions, F and D
0:42extensions. F is for 32-bit floating
0:45point, and D is for 64 floating point.
0:48Uh these are the extensions, FD and Q. Q
0:52is 128-bit extensions, but no one is
0:55using 128-bit. 64-bit processors are
0:58enough for the current world. For this
1:00reason, there is no commercial 128-bit
1:03processor.
1:04So, in RISC-V,
1:07I mentioned that RISC-V has 32
1:09registers,
1:11but these registers are for integer
1:13values. If you want to also add a
1:15floating point uh
1:18instruction unit to your processors, you
1:20need to put also another set of register
1:23for floating point values. So, if you
1:26want to implement F and D
1:29extensions to your RISC-V processor, you
1:32need to add also another 32 32-bit
1:35registers
1:36to keep the floating point numbers.
1:38Because floating point numbers has
1:39different set of registers.
1:42So, in here, with is the highest
1:44precision. For example, F is implemented
1:47RF RVF implemented. This is the 32-bit.
1:52So, this is the floating point register.
1:54It starts from still same.
1:56Uh it starts from FD0 to FD F sorry F0
2:02to F31 but no in here F0 is not zero. F0
2:08can not can be different than zero. This
2:10is special case for the integer.
2:12So F0 it is all
2:15any value. It can keep any value between
2:17F0 and F31.
2:19So there are different floating point
2:22instructions.
2:23They are not important for this class,
2:25but I can just briefly say that for
2:28example addition, subtraction, division,
2:30square root, min, max.
2:32Uh there are some more instructions. For
2:34example, you can do an floating point
2:36operation. For example,
2:38you can do there are some floating point
2:41operations that you are doing operation
2:43between a floating point number and
2:45integer number. It uses for example an
2:48operand from integer register file.
2:51There are conversion operations. So in
2:54here for example, we have an example C
2:56code. Uh float we are if you're writing
2:59a C code and you
3:02define the variable as a float, then
3:05it runs the it does the operations on
3:08this variable as floating point.
3:11So in here for example, I have a scores
3:13array 200 size and in this for loop I am
3:17adding 10 point to each of them.
3:20So this is the risk-5 assembly code
3:22correspondence for it.
3:24Uh so in here I have a variable loop
3:26variable I. I starts with zero. So I
3:29assume that I is stored in S1 register.
3:32So I'm initializing it as a zero and
3:36T2 is another register.
3:39It keeps the maximum value 200 in here.
3:42And I have also another value 10. This
3:45is constant. I am keeping it in a T0
3:48register.
3:50This is the initialization.
3:52And in here
3:54I'm doing the
3:57uh this this this
4:00operation
4:01is converting this T0 register 10.
4:06This integer T0 value to floating point.
4:10So, this 10 integer 10 becomes floating
4:12point 10. So, this T0 10 is assigned to
4:16FT0 register. FT0 is a floating point
4:19register.
4:21So, it is
4:22uh signed word size.
4:25And
4:27in this for loop, for example, I am
4:29doing comparison. I am checking whether
4:32S1 becomes T2. T2 means 200. So, S1 as
4:36one at the beginning it was zero. So,
4:38I'm comparing
4:40branch greater or equal. So, comparing
4:42whether S1 is uh
4:44greater or equal to T1. I'm just doing
4:47this this
4:48calculation. And if it is so, I am
4:52jumping to down section, but if not
4:55I I continue from here.
4:58In here, I am doing uh shift left
5:00logical immediate.
5:02So, in here, I have a address, for
5:05example, in here S1 is an address.
5:08I am just multiplying it by four.
5:12Uh
5:13and adding it to T0.
5:23Okay, in here S1 is multiplied by four
5:27because this is
5:28shift left logical immediate. Sh- It
5:32means that multiply by four and writing
5:34it to T0.
5:36And this T0 is added by S0.
5:39So,
5:41S0 actually keeps the
5:44address of this array. So, S0 assume
5:48that S0 is the address of this array.
5:51So, at each time I am doing a floating
5:54point load operations from this
5:57value, T0 value.
6:00And doing the addition operation, it
6:02means that increasing it by 10 and then
6:04storing it back to the same location.
6:07This is floating point load word. This
6:09is floating point store word. I'm
6:12storing it back and then increasing the
6:14array pointer by one. And each time I am
6:17checking whether I I I am over the limit
6:20or not. If under the limit, I continue
6:22to run it. Uh the important point in
6:26here is that
6:27since memory is byte addressable and
6:30each time I am accessing a word
6:33in this case, while accessing this
6:36scores
6:37for example
6:38if I access score zero
6:40I assume that I access score zero
6:43after accessing score zero, if you want
6:46to access score one, you need to
6:47increase it by four. Because at each
6:50time this is word operation, I am
6:52accessing the four bytes. For this
6:54reason why I am doing in here multiply
6:56by four. So for example, scores one at
7:00point zero, scores one zero, sorry, at
7:04location zero, one at location four, two
7:08at location eight
7:09three at location 12. So, each time I am
7:13multiplying this
7:15array index by four to access the actual
7:17location of this word. Is it clear,
7:19right?
7:23Okay, this is floating point. Floating
7:24point is not important. It's just an
7:26introduction. We we will not deal with
7:29floating point in this class. And we
7:31will not implement floating point
7:32register also in our processor. We will
7:34only focus on the in integer part.
7:42So, at that point we can a break. This 4
7:44to 5 minutes. We can give a break 10
7:47minutes.
7:48And during that time also you can do
7:51quiz. You can do quiz. This quiz is
7:55is not assessing the your knowledge.
7:59It is just to know you, why you are
8:02taking this class.
8:04So, you can answer
8:07during the break.
8:10So, when you answer it, everyone will
8:13get 100.
8:15Because there is no correct answer.
9:08So, we can continue.
9:10There is also another extension named C
9:12extension.
9:14Uh I told you that all risk-5
9:17instructions is 32-bit, but this is not
9:21correct.
9:22Uh
9:22if you are using the C extension, then
9:26you can compress the instructions to
9:2816-bit also, but in some cases, not
9:31always.
9:32Uh if you are using the C extension,
9:35some instruction can be compressed to
9:3716-bit, but not 32.
9:40Either 32-bit or 16-bit.
9:44So, this extension is used for this
9:47purpose. So, some instructions can be
9:49decreased to 16-bit,
9:52but not all.
9:54In this case, I told you that in
9:58normal RISC-V, at each each instruction
10:0132-bit, so each time when I while
10:04switching to PC,
10:06I am adding four to two PC because it is
10:0932-bit, but in
10:11compressed version,
10:13if I run a compressed instruction, then
10:17next instruction is after PC plus two,
10:20after two bytes. Because instruction if
10:23instruction is compressed compressed, it
10:25is 16-bit instruction. So, the next PC
10:28is PC plus two in this case.
10:31But, not all instructions can be
10:34compressed. Only some of them can be
10:36compressed.
10:37So,
10:39it can replace common integer and
10:40floating point instructions with 16-bit
10:43values. Why people are doing it?
10:46Because assume that, for example, you
10:48compile a program, and this program is
10:5040 kilobyte, for example.
10:53And assume that some instructions can be
10:56compressed in in this program, so you
10:58can reduce its size to 30 kilobyte, for
11:01example, or 20 kilobyte, maximum 20
11:03kilobyte.
11:04So, it is people use it to to compress
11:07the instruction so that your compiled
11:10code is size of the compiled code is
11:12less than the uncompressed one.
11:16So, this is important because, for
11:17example, if you are using a
11:19microcontroller, and it has a limited
11:22space, then compressed version keeping
11:26the compressed instructions is nice
11:28because you are using less space.
11:31You have You need less memory
11:34requirement then.
11:36To compress instruction uses prefix C.
11:38For example, at this is 32-bit
11:42instruction.
11:43If you have a
11:46compressed version of this one, then it
11:48is C.at.
11:50It prefixed with C.
11:53And for example, in here the same code,
11:56this time I defined the scores as
11:59integer. So, if it is integer, then it
12:01means like this is integer scalar
12:04scalar integer.
12:06So,
12:08when I compile this code,
12:10then it generates the
12:12normal add instructions.
12:15And assume that while while compiling
12:19this code, I told that my processor also
12:22can
12:23support supports the C extension. So, it
12:26can run the compressed instruction also.
12:28By the way, this is optional. You can
12:30say that my processor is not supporting
12:32C extension, then no problem. All
12:35instructions becomes 32-bit.
12:37But if you want to compress the compiled
12:39programs and can be able to run it, then
12:43you need to add C extension. And assume
12:45that in here I compiled my program with
12:47C extension. And in this C extension,
12:51some of the operations can be
12:53compressed. Some of the instructions can
12:55be compressed and it's putting the
12:58compressed version of this instruction
13:00in this case.
13:05So, this is the same example program.
13:09So, in here there are some cases. For
13:11example, this add immediate, the
13:13compiler
13:15couldn't compress it because 200 was
13:17very big to fit in a compressed
13:19immediate format. Normally, instructions
13:2232-bit, but if you are compressing it,
13:24it is 16-bit. But in here
13:28200 is
13:2912-bit immediate value. The remaining is
13:334-bit, so it is impossible to fit this
13:35value.
13:36So,
13:37the compiler couldn't compress this
13:39instruction, for example, but it could
13:41it could compress this
13:43load immediate one.
13:47Uh
13:47c.l.i.1.
13:49This is initialization. Actually, it was
13:51at There you see it was at. I was doing
13:53s10
13:54uh zero. So, and initializing s1 as
13:57zero. It put another instruction named
14:00as c.l.e.
14:02For example, this is the load word
14:04version, but compressed one.
14:06So, in here I am doing the same
14:08operation, but I use the compressed
14:11version of it.
14:14For example, c.add immediate s04 is
14:16equivalent to add immediate s0 s04, for
14:19example.
14:21Also,
14:22this branch greater or equal couldn't be
14:25compressed, so in here we also couldn't
14:27compress it.
14:30How
14:31it is compressing? Actually, in
14:33compressed instructions, for example,
14:37uh
14:38compiler is doing so. In RISC-V
14:40specification, I can give further
14:42information. While
14:44in for example, compressed specification
14:46says that
14:48for example, if the register that you
14:50are using is between Assume that it is
14:52x0 and x7. Assume that. In this case,
14:563-bit is enough for register, right?
14:59Uh it says that if
15:01the operation is compressed,
15:03then register can be between zero and
15:06seven.
15:073-bit only. So, it separates only 3-bit
15:09for compressed instruction.
15:12But, for example, if you are using any
15:15register like x27,
15:18then it cannot compress this
15:19instruction.
15:21This is a special format.
15:24So, I will briefly mention about the
15:26privileged instruction set architecture.
15:28As I told you, privileged instruction
15:30set architecture is for the operating
15:32system.
15:33Uh but I am to mention it because there
15:35are some concepts that we need to take
15:37care, pay attention
15:40uh while looking to out-of-order
15:42processors. We will see later. For this
15:44reason, I will mention briefly about
15:45privileged instruction set architecture.
15:48But privileged is for running operating
15:50system.
15:51So,
15:53in RISC-V, there are privileged levels
15:55for operating system support.
15:58Uh generally, in a processor,
16:01processor is a machine. There is a
16:02machine level. Machine level is the
16:05uh lowest level. And in machine level,
16:08you can run anything. No protection.
16:11Uh because machine is the processor
16:12itself.
16:15One
16:16level upper, there is supervisor mode.
16:19And in this supervisor mode, uh
16:22operating system runs.
16:24And on top of the
16:26operating system, user programs run. For
16:28example, in this laptop, I have
16:30PowerPoint presentation. And this
16:32PowerPoint presentation runs on the uh
16:35user mode. In this user mode, for
16:37example, I have PowerPoint presentation.
16:41And in this laptop, I have Windows
16:43operating system. Windows operating
16:45system. And assume that this Windows
16:47operating system is running on RISC-V
16:49processor.
16:51So, PowerPoint is the user
16:54application that I am running.
16:56Uh Windows is the operating system
16:59running this PowerPoint.
17:00So,
17:02this privileged levels are required
17:04because
17:06this PowerPoint, for example, assume
17:08that PowerPoint is running, but at the
17:10same time, WhatsApp is running in here
17:12at the same time.
17:14This PowerPoint to don't access the data
17:17of WhatsApp. For this reason,
17:19while accessing the machine, we are
17:22going through the operating system and
17:25asking
17:27permission.
17:29So, for example, this PowerPoint says
17:30that I am running I am reading a data,
17:34for example, PowerPoint slides. I am
17:35reading this data. Can I read it? It
17:38asks the operating system. And if
17:40operating systems gives permission, then
17:43it can access the file and show us the
17:45presentation. Similar manner,
17:47WhatsApp, if it wants to access the
17:50data, it asks the operating system. In
17:52this way,
17:54assume that WhatsApp wants to access the
17:57data of PowerPoint, the operating system
17:59doesn't allow it. That's why there are
18:01privilege levels and this privilege
18:03extension of RISC-V defines these
18:05privilege levels and its standards.
18:08Uh this is a
18:09operating system concepts in a nutshell
18:12in a basic
18:13uh way.
18:15RISC-V has privilege levels for
18:17operating system support. Uh the
18:19architecture has many control and status
18:22registers
18:23uh in addition to normal register file.
18:26So, I mentioned you about the register
18:28file between X0 and X31. If you want to
18:31support operating system, you have to
18:33support different kinds of registers
18:35also.
18:36Uh but this is a different story.
18:39So, privilege levels limit access to
18:41memory or set certain instructions.
18:44Uh so, RISC-V privilege
18:46uh modes, as I told you, machine mode,
18:49it is the machine itself, the processor
18:51itself. It is the mode like you can
18:53access everything. No no Even you are
18:55not in machine mode, you are not asking
18:57any
18:58uh permission.
19:00Uh system mode, it is the supervisor
19:02mode, it is the operating the mode that
19:05operating system runs. User mode, the
19:07mode that we are running our own
19:09software as the user.
19:12There is a hypervisor mode, but this is
19:14different. No need to mention about it.
19:16Uh and
19:18all these
19:20privileged modes has some special
19:22registers that you are changing these
19:25registers to get access or to ask access
19:29to check whether can I access or not.
19:32These are all special registers. No need
19:34to
19:35worry about them.
19:37This is just a
19:38uh
19:39brief introduction.
19:41So, you will not also see. We will not
19:43see because we we are going to focus on
19:44the processor architecture itself. We
19:46will not uh
19:48go into these details. We will not deal
19:50with them.
19:52The important point in here is that for
19:54example, I told you that
19:57for example, I have a application in
20:00here.
20:01I have WhatsApp application and
20:04E-Nabu's application.
20:06E-Nabu's application has very sensitive
20:08information, health information for you.
20:11And WhatsApp is also working in here.
20:14In here,
20:15the important point that I told you is
20:18that while accessing the data,
20:21these two applications request access
20:23from the operating system. If operating
20:26system allows the access, it can get the
20:28data.
20:30So, what about assume that WhatsApp, by
20:32the way, made by Israel,
20:34wants to access your health data.
20:37It can access.
20:39In this way, it asks to operating system
20:42to access the data of this application,
20:44health application.
20:46And in this case, if it tries to
20:49access,
20:52operating system doesn't allow it and
20:55gives exception. It's named as
20:57exception.
20:58Because it has no right to access that,
21:01so it generates an exception.
21:03So, this concept is called as an
21:05exception. If you are trying to access a
21:08data or something and you have no
21:12right to access it, you are your program
21:15gets a exceptions. So, this
21:17exception is important exception
21:20concept is important. Exception means
21:22that unscheduled function to exception
21:25handler.
21:26Exception actually leads to unscheduled
21:28function call to exception handler.
21:32So,
21:34by the way, this is exception
21:37and there is also another kind of
21:40concept. It is interrupt.
21:44Interrupt is also
21:46Interrupt is not like exception.
21:48Exception is a problem problem. It says
21:51that there is a problem, so operating
21:52system needs to take care of it because
21:54for example, WhatsApp tries to access
21:56the some important data,
21:59but at that point operating system takes
22:01the control and manage this situation.
22:03But there is also another concept. It's
22:05called interrupt.
22:07Interrupt is the
22:09It is interrupt actually. So, it is like
22:12for example, when you press a keyboard
22:14keyboard, it's an interrupt to the
22:17processor.
22:18For example, while I am moving this
22:20mouse, it is an interrupt. It says that
22:24it says processor that user
22:26entered some data to the processor or
22:29user
22:31user did something. So, you need to be
22:34careful. You need to take care of what
22:37user is doing.
22:39So, this is the interrupt concept. But
22:41both exceptions and interrupts are
22:43classified as trap and trap means that
22:46the
22:47operating system needs to take control
22:50and do the according function. Do the
22:53according take the according actions.
22:55This is named as trap and trap is can be
22:59either exception or
23:01interrupt. Trap source can be either
23:03exception and interrupt.
23:06Exceptions can be synchronous by the way
23:10and can occur at run time and it is
23:13always associated with an instruction.
23:15For example, if you want to access a
23:16region and you have no access right,
23:19then it is with load operation because
23:21load operation generates this exception.
23:23It tries to load a data
23:25and then
23:26if it cannot load, it generates an
23:28exception. Interrupt is asynchronous.
23:31Like for example, this mouse click is
23:33this is for example interrupt. For
23:35example, this is interrupt. This is
23:36interrupt.
23:38So, it is asynchronous. We don't know.
23:40At any time it can happen. So, it is
23:43triggered externally like the user input
23:46and it is not associated with an
23:48instruction.
23:50So, but both of them
23:53is classified as a trap and trap means
23:55that the transfer of control to a trap
23:58handle caused by either an exception or
24:00interrupt.
24:03So,
24:04exceptions are caused by hardware.
24:08If caused by hardware, they are called
24:10at interrupt like keyboard press and if
24:13software,
24:15for example, while running an
24:17instruction
24:19processor read an 32-bit value, but it
24:23couldn't find the type of instruction
24:25for example. It is not add
24:27nor sub. So, we don't know the type of
24:30this instruction. So, it is undefined
24:32instruction. In this case also we are
24:33generating an exception because we don't
24:35know. We start we are running the code
24:38and we saw a
24:39instruction in code and we don't know
24:41what what it corresponds to. So, this is
24:43also kind of a
24:45exception.
24:46So, in a processor when exception
24:48occurs, the processor
24:50records the cause of the exception,
24:52jumps to the exception handler, and
24:54returns to the program. This is the all
24:57operating system is doing. Actually, all
24:59processor is doing. Whenever you reach a
25:02cause and see an exception, we are doing
25:05these steps.
25:09So, in order to handle the exception,
25:11there are different
25:13registers. No need to worry about them.
25:15They are not important. But, whenever we
25:17solve an exception, we are switching to
25:19M mode and in M mode, we are handling
25:23this exception. This is the important
25:25point.
25:27Uh there are some special
25:29control and status registers to handle
25:31the exceptions, but no need to deal with
25:34to go into the detail with them because
25:37they are not much important in this
25:38class. But, you need to just need to
25:41know the concept of trap, exception, and
25:44interrupt. This is the important because
25:46while looking to the out-of-order
25:48processors, these concepts will be
25:50important. For this reason, I am trying
25:52to teach you.
25:55So, whenever a processor detects an
25:57exception, it jumps to exception
25:59handler.
26:00And this exception handler then
26:02does the corresponding takes the
26:06corresponding actions.
26:10So, in here there is an example, but if
26:13you want you can inspect it, but no need
26:15for you for you right now. This is just
26:17an exception
26:19topic. And there are different kind of
26:21kind of exceptions. For example, if
26:23instruction address misaligned is this
26:25is an exception. For example, you are
26:27run trying to run an instruction
26:30uh but you have no access to in this
26:33instruction location in memory. This is
26:35also an exception. If the instruction
26:39that you read is illegal, you don't know
26:41what is it. This is illegal.
26:43Uh there's breakpoint. While
26:46the trying to do load,
26:48you can generate exception also.
26:52Uh in here there's an exception called
26:54handler example. If you want you can
26:56inspect at home, but no need to worry
26:59about it right now. This The important
27:01one is the exception concept in here
27:03because later we will see it
27:06in while
27:08looking to the auto folder processors.
27:11So, until now I
27:13show you the
27:15instructions,
27:17but I didn't mention about the S uh
27:20binary correspondence of these
27:22instructions. I show you assembly
27:24language instructions that we can read
27:26and understand. For example, like add,
27:28sub, uh shift less than, branch greater
27:31equal.
27:32Uh but there must be machine language
27:36correspondence of these instructions.
27:39Because
27:40computers are not reading like us. They
27:43are not looking to add add and
27:45understanding whether it is add.
27:48Computers are just looking to ones and
27:50zeros.
27:51And we told that in RISC-V
27:54each instruction
27:56is represented as binary and computers
27:59only understand ones and zeros.
28:01So, if the instruction is 32-bit,
28:05uh
28:07actually it reads 32-bit value and tries
28:10to try to understand what this 32-bit
28:14value represents as an instruction.
28:17RISC-V instructions are 32-bit if it
28:20supports compressed, it is 16-bit,
28:23but it's always 32-bit. By the way, in
28:26Intel, for example, instructions are
28:28variable. In Intel, for example, since
28:30this is a CISC architecture,
28:31instructions between 1 byte and
28:3516 or 17 byte between them. The
28:37instruction size is also changing in
28:39Intel, but in RISC-V instruction size is
28:42always
28:4432-bit. If you are supporting C
28:46extension, then it can be also 16-bit.
28:50In overall, there are four types of
28:52instruction formats. There are more
28:53types, but no problem. We can assume
28:55that there are four types of instruction
28:57types. R-type, I-type, S-type,
29:00and U-type.
29:03So, we can expect that R-type is the
29:07instruction type for register type
29:09operations. So, you remember
29:11Remember, there are some operations.
29:13This is the op code for example. And
29:16this op code is doing operation on these
29:19two registers. One of them is for
29:21example X2, X3. And result is going to
29:25X5, for example. It is doing some
29:28operation on X2 and X3 and resulting the
29:31result to X5. This kind of operations
29:34are R-type operations. And R-type
29:37operations are decoded
29:40encoded in a 32-bit instruction format
29:43in this way.
29:45So, in R-type operations, RS1, RS2,
29:48these are the source register. RD is the
29:50destination register. There are other
29:52fields, op, the operation code or op
29:54code, and there are function seven and
29:57function three fields. Function seven
29:59means it is a 7-bit.
30:01And function three is 3-bit.
30:04So, this op function seven and function
30:07three
30:08corresponds to the actually operation to
30:11be performed.
30:15to be performed.
30:17So, this is the 32-bit
30:20encoded operation format.
30:24Between This is
30:26between zero and 31-bit. So, when you
30:30look at this R-type operations, RD is in
30:33this field. In this 32-bit value, RD is
30:36between
30:37seven and 11 registers bit fields. RS1
30:41is between 15 19, and RS2 is in here.
30:44And op function three and function seven
30:47is stored in here in this location.
30:4925-31, 12-14, and 06.
30:54So, op function three and function seven
30:57describes what this operation is doing
31:00and this RS1, RS2, and RD are the
31:03register
31:04values. So, these are the five bits. Why
31:07it is five bits? Because I have 32
31:09register. 2 to the
31:11five is 32. So, I am encoding these 32
31:15values by five bits. For this reason,
31:17these are five bits values.
31:20So, this is the R-type coding. So, these
31:22are the examples. For example, addition,
31:25subtraction operation. When you look at
31:27it here, for example, for addition,
31:29function seven field is zero, function
31:31which field
31:32function three field is zero, operation
31:35field is 51.
31:36For example, for sub,
31:38operation is 51, function three is zero,
31:41but function seven is 32.
31:44But, whenever function seven is 32, it
31:46is sub. It is function zero with this
31:49function three and operation values,
31:51then it corresponds to add.
31:54So, this is for coding. For example, for
31:56add and sub instructions. And this is
31:59the binary versions. For example, if RD
32:01is 18, then when you look at here, this
32:0410010, it is corresponds to 18 in
32:07register. These are the exact 10
32:10representation. And
32:12in this in memory, we are storing these
32:15values and each time PC increases and
32:18runs these instructions. And cause this
32:20is we will encode
32:22Actually, we will decode these
32:23instructions and understand what this
32:24instruction is doing while this while
32:27designing our processor. We will not
32:30start
32:31We We don't start to design the
32:33processor. We will do it maybe we will
32:35start to do it maybe after two two
32:37weeks. Two or one weeks.
32:42So R-type
32:43it is the operations for op, for
32:46example, rd
32:48rs1 and immediate. For such kind of
32:52operations it is a R-type operation.
32:55And uh
32:56I-type operation
32:58three operands rs1, rd, and immediate.
33:01Uh it has no function seven.
33:04It has op and function three field and
33:06it is enough to
33:08uh corre- it is enough to encode to
33:11uh
33:12corresponding functionality.
33:14So, this is the I-type operation format.
33:20So, here there are I-type operations.
33:22Load, by the way, load are also I-type
33:26operation and this add immediate
33:28operations are I-type operations.
33:32SB-type it is used for store and branch
33:35operations. It has 12-bit immediate, by
33:39the way, still.
33:40Uh
33:41but it differ only immediate encoding.
33:43This is S-type. S-type operation in here
33:45function three in here.
33:47Immediate is a little bit different.
33:50The
33:51bits between 0 4 in here and 5 11 in
33:55here for S-type and for B-type
33:58it's a little bit distributed.
34:00And there is a reason why this is so.
34:03Uh because RISC-V tries to always put
34:08depending on the operation type
34:10irres- irrespective of the operation
34:13type, actually.
34:14Whether it is SB, I, or R these RS1
34:18fields are always in the same location.
34:20They try to keep these RS1, RS2 in the
34:22same location.
34:24Uh this is very good because at the end,
34:27while reading the RS1, whether it is SB
34:30or
34:31other types, you are always reading it
34:33from between 15 and 19. And while
34:36designing the processor hardware,
34:38this really increases the speed of the
34:41decode unit, your decode unit.
34:44But in B type, immediate is a little bit
34:46distributed, so you need to collect them
34:49while
34:50designing your processor.
34:54S type is This is a S type detail.
34:58Uh This is the operation. In here, there
35:00are S type operation examples.
35:02Uh store word, store half, and store
35:04byte. So, you can see it in here.
35:07Function three in here, for example,
35:10corresponds whether it is word, half, or
35:12byte.
35:14It's op op code is same, but depending
35:17on function three, its size is changing.
35:23This is B type, branch type operations.
35:26It is immediate is a little bit
35:28distributed. So, for example, immediate
35:31one
35:33between one four in here
35:36between five to 10 in here, then 11 is
35:39in here, and 12 in here.
35:41Why it is so?
35:43When you start to read the RISC-V
35:47uh
35:48extension documentation, you can
35:50understand because they are trying to
35:52keep the same field in the same location
35:54always. For example, in here, in RISC-V,
35:57they are always keeps the high
36:00significant bit in here at the end of
36:02the
36:03instruction in this 31-bit
36:06because it is very good while
36:10for example, if you want to do sign
36:11extension to immediate, you are you can
36:14always get it from this location. So,
36:16you can you will see that while
36:17designing the hardware, it makes
36:19everything easier.
36:23Uh by the way, branch
36:26has immediate between one and 12. It is
36:2912-bit immediate, but it has no zero
36:32bit.
36:33Uh because in branch type operations
36:38I can either jump to across 16-bit or
36:4232-bit boundaries.
36:45So, if
36:47I assume that if I am supporting
36:48compressed instruction, if I am jumping
36:5216-bit
36:54boundaries, then my least significant
36:57bit is always zero.
36:59Because this is byte addressable, and
37:01while changing the PC
37:04in compressed format, if I am supporting
37:07the compressed, my the least significant
37:10bit of the PC always is zero
37:13in byte addressable memory because at
37:15each time I am increasing the PC by 16
37:18by 6 6 by 16 or 32, and at each time the
37:23least significant bit is always zero. In
37:25this case, so there is no need to put
37:28another zero to immediate. So,
37:31in this case, for example, you can
37:33assume that implicitly there is a zero,
37:36and then you can just encode to between
37:401 and 12 for this field. So, you can use
37:44one more bit, actually. So, instead of,
37:47for example, because in in the
37:49instruction format, you have 12-bit
37:52available
37:53after this op function three registered,
37:57the left is 12-bit.
37:59And instead of using this 12-bit to
38:02encode between zero to 11
38:05while
38:07adding this
38:09uh immediate to PC,
38:11since its first bit is always zero,
38:15I can just encode it as between 1 and
38:1812. So, implicitly it is like keeping
38:2113-bit because it's
38:24least significant bit is always zero.
38:26So, I am assuming that least significant
38:27bit is always zero. So, I am storing it
38:30in here in between 1 and 12 in here. So,
38:34in this way I can jump between 13 bit
38:37values. Is it clear?
38:44So, this is the B type operations.
38:47B type is similar also because while
38:50switching the PC, the least significant
38:53bit is always zero. So, it's immediate
38:55field is also starts with one.
38:57And this is the encoding for B type. So,
38:59you you can inspect at the home. This is
39:01for example branch equal operation
39:03correspondence.
39:06Uh U or G type, it is upper immediate
39:08type. Upper immediate type is for load
39:10upper immediate. And there is also
39:12another instruction at upper immediate
39:14to PC. And these kind of instructions
39:17are using upper immediate type.
39:19Uh
39:20it's It has a huge immediate, 20 bit
39:24immediate.
39:25For this reason, 20 bit of this 32 bit
39:28value is separated for immediate and the
39:31rest is for opcode and
39:34destination register. And that's all.
39:37It can keep huge immediate. But look at
39:39always immediate fields are same in this
39:42operations.
39:45It has U and G type.
39:47The difference is between the
39:49immediate fields actually. This G type
39:52has distributed immediate. You can you
39:55you need to collect it while designing
39:56your CPU.
39:58And these are the examples for U type
40:02load upper immediate uh format. You can
40:04inspect it in detail.
40:07Uh G type is also similar but immediate
40:10is a little bit different. There is
40:11still op and rd field in here.
40:15And in here I have immediate field.
40:19And this immediate is also starts with
40:21one.
40:24Because in PC relative jumps, least
40:27significant bit is always zero.
40:36Uh
40:36by the way, jump and
40:40jump
40:41and link
40:44register operations are I type, not J
40:47type. Because in jump and link register
40:50operations, I have register field also
40:53as a RS field. So, this is I type.
40:56I don't know whether there's an example.
40:59Uh there's no example in here, but you
41:01can inspect
41:02JAL
41:04R operation, jump and link register
41:06operation is I type. Because it has a
41:0912-bit immediate, and it has a RD field
41:12also.
41:13So, in order to
41:15separate a place, reserve a place for
41:17this RD, its immediate is less than 20.
41:28So, in here there's an uh
41:30JAL operation.
41:33Yeah, this is this is Okay, this is JAL
41:35operation.
41:36Uh it is a it is jumping to function
41:38one.
41:39And also
41:41keeping the return address at RA RA
41:44register. RA maybe X2, X3, I don't know.
41:48You you can check it.
41:50So, this is the corresponding assembly
41:52for the encoding. So, this is the
41:54immediate field.
41:56So,
41:58when you look at here, this function one
42:00is
42:010x A67F8
42:04bytes past JAL. So,
42:07I'm keeping this value in the immediate
42:09field.
42:11Uh
42:13and this is a opcode.
42:15In here, if opcode is 111, then it means
42:19that this is a jump jump instruction and
42:22its RD is
42:24one.
42:25It means that RA is X1, actually. So, it
42:28is one because
42:33So, do you have any questions about this
42:36RISC-V
42:37uh encodings?
42:41You can ask in Turkish, also.
42:43If no question, we can finish at this
42:46point.

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