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W3 RISC V ISA I Part1 EN — Transcript

by Hasan Erdem Yantır · 11,868 words · 2,187 segments · language en · Watch on YouTube

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0:07So, starting from the this week, we are
0:10going to start to see the risk five
0:12instruction set architecture.
0:14As I told you previously, instruction
0:16set architecture defines how the CPU is
0:18controlled by the software.
0:20And it was the common language between
0:22the hardware and software.
0:26So, it is just actually
0:28instruction set architecture means
0:30assembly language for a processor.
0:35And in this class, we are going to focus
0:37on microarchitecture and architecture
0:39implementation of a risk five processor,
0:42which is a which will be a complex
0:44processor.
0:46Uh
0:47But as I told you before,
0:49there are layers, there are hierarchical
0:51layers. It starts from physical devices,
0:54devices which are formed to they are the
0:57transistors, transistors forms to analog
0:59circuits, digital circuits, logic.
1:01And after that,
1:03by using the logic circuits, we are
1:05building the processors. But in this
1:07course, we will not deal with the logic
1:09circuits. We will write hardware
1:11description language, which is a which
1:12is a kind of also abstraction.
1:16And by describing our processor, we are
1:19going to build microarchitecture. And
1:21this microarchitecture will obey the
1:24risk five architecture.
1:26In here, there are two architecture
1:28terms. One of them is architecture. This
1:30architecture means that
1:32people say it as big A architecture,
1:36capital A architecture, big A
1:38architecture.
1:39And it is the instruction set
1:41architecture actually.
1:43And microarchitecture means
1:45implementation of this architecture.
1:47There is a slight
1:49meaning difference between them, between
1:51the architecture and microarchitecture.
1:54For example, in Intel processors, for
1:56example, there are i3, i5, i7, and
1:59different variety of Intel processors.
2:02They are all different kind of
2:03microarchitectures, but it is its
2:06architecture is x86, Intel x86
2:09architecture. But microarchitecture
2:12changes. So, in this way, there is a
2:15standard architecture,
2:17and
2:19but with respect to this standard
2:20architecture, there are different kinds
2:22of processors,
2:23and all these processors can run the
2:26same assembly code, because architecture
2:28is constant. It's a standard, and
2:30microarchitecture is changing. There are
2:32different variety of processors, but
2:35they all can all run the same program.
2:38This is the difference between them.
2:40So, yeah, regarding that, for example,
2:43software developers
2:44does not care don't care whether it is
2:47i5, i7,
2:49uh
2:50so, they can just obey the arc-
2:53architecture, which means the RISC-V,
2:56and it can run
2:57in any hardware. So, for the software
3:00guys, the important one is
3:04change it.
3:06For the software guys, the important one
3:08is the which instruction set
3:10architecture
3:12which they are developing the software
3:14for, and for the hardware guys, in here,
3:16there are different kind of processors,
3:19i5, i7, i3. Even for RISC-V, there are
3:22different kind of RISC-V processors.
3:25Since this instruction set architecture
3:27is defined between them,
3:29then this software can run on any
3:32hardware
3:33implemented by this instruction arc- set
3:36architecture, but all for the hardware
3:39guide, which is us, we are the hardware
3:41guys, for the hardware guys, it doesn't
3:44matter
3:45as long as the instruction set
3:47architecture is the same. So, in here,
3:49we can implement, for example, in here,
3:51there are around 10 10 hardware
3:53architecture guys. You can implement all
3:55your processors differently, but a a
3:58software guy can run
4:01the software we develop
4:04on all of these processors. He can He
4:06can run it.
4:08So, this is all these different kind of
4:11implementations are named as
4:14microarchitecture, and this is people
4:16say it as a big A architecture or just
4:19architecture.
4:22So, architecture is the programmer's
4:24view of computer defined by instruction
4:26and operand locations. It is just
4:28assembly language. And
4:29microarchitecture's the how is the how
4:32to implement an architecture in
4:33hardware. This is our job.
4:37As I told you before, there are two
4:39kinds of instruction set architectures.
4:41One of them is RISC and other one is
4:42CISC. There are different varieties, but
4:46these are the most common ones. Maybe
4:4899.99%
4:50of the processors are following either
4:53of these two.
4:56For RISC, there are two varieties,
4:58RISC-V and ARM. ARM is a commercial. You
5:01cannot build a
5:03You can read the ARM documentaries, but
5:05you cannot build a processor by
5:07following ARM instruction set
5:09architectures because you have to pay
5:11money. This is their their
5:13property.
5:15RISC-V is a open-source one. It is like
5:18the
5:19Linux version of hardware.
5:22CISC is mainly X86, and AMD and Intel
5:26processors are following CISC.
5:29And well, this is a
5:31rough comparison between these
5:32instruction set architectures. For RISC,
5:35it is basic and simple instructions. It
5:37generates code because since
5:39instructions are simple,
5:40if you want to build a task,
5:43compiler generates more code because
5:44instructions are simpler.
5:47Uh, but it
5:49Uh,
5:50by following the RISC-V instruction set
5:52architecture, you can build more area
5:55and power efficient cores. It is good
5:57for mobile. And by the way,
6:00uh, you know,
6:01Apple is also building ARM processors,
6:04which is a kind of RISC, uh, instruction
6:07set architecture type.
6:09And these processors are actually
6:12outperforming Intel right now. So,
6:16it's showing more performance than Intel
6:18processors. So, for this reason,
6:20RISC-based instruction set architectures
6:23are start to extend the high performance
6:25computing. So, you can build a
6:27uh,
6:28laptop and even server processors by
6:32using RISC.
6:33And CISC, it is
6:35advanced, yeah. Instructions in CISC are
6:38more advanced. It's complex. It it
6:40yields more lower code size, but it's
6:44implementation implementations are
6:45generally area and power hungry.
6:48Uh, it's not good for mobile. For this
6:51reason, there is no processors running
6:54There is no mobile phones run by
6:57Intel processors. There is no mobile
6:59Intel processor because it is power
7:01hungry.
7:04So, this was a summary. These two slides
7:06was a summary.
7:08So, in here, we can do an introduction
7:10to the computers. How programs compiled?
7:14Normally, the software people writes a
7:16high-level code, for example, C, C++,
7:20C#. And compiles it.
7:23And this compiler change converts it to
7:26assembly code.
7:28Uh, assembly code is the like defined by
7:31instruction set architecture. Assembly
7:32code is actually is
7:35instruction set architecture.
7:37And by using the assembler,
7:39we convert it
7:42By using assembler, uh, we convert it to
7:45an executable format and load it to the
7:48memory.
7:50And
7:51processor reads that the program from
7:53memory and run its
7:55instructions.
7:58In here there are different some steps
8:00like a linker. For example, if you are
8:02using another standard functions,
8:05you can use linker and this linker also
8:09adds the location of the function that
8:12you called outside of the this program.
8:19And loader in here loader also loads the
8:21program to memory and this after that
8:24your program your compiled program
8:26inside the memory
8:28and in there processor runs the
8:31instructions one by one.
8:34So, when I compile the high-level code,
8:37what is stored in memory? Instructions
8:39are stored.
8:41It's called also as text.
8:43And data is stored because in in a
8:46program I have instructions and these
8:49instructions are working on data also.
8:51It's they are processing data, so there
8:53is also the data section. So, a compiled
8:56program has instructions and data.
8:58Of course, some of the data are coming
9:00from outside, for example, from keyboard
9:02or disk,
9:04but
9:05generally at the beginning
9:08compiled program includes some initial
9:11data.
9:12And this data is
9:14actually put either global defined as a
9:17global static, so they are allocated
9:20before program begins, or dynamic
9:22allocated within the program. While
9:23program runs, it allocates it.
9:28So, in here for example,
9:30this is a memory snapshot. It starts
9:33from address zero and goes until 0x
9:37FC.
9:38And in this memory, for example,
9:41in here
9:43there is operating system
9:45codes and IO IO
9:48regions. Operating system code is in
9:51here, for example, if you're you are
9:53running Linux Linux in here, Linux
9:55instructions.
9:57And if you want to put your program into
10:00memory, for example, you are putting it
10:03text section. Text it is because
10:05instructions are called as text.
10:08This here
10:09people, for example, in here, we can put
10:11to instructions to here.
10:14If we have data, we can put to global
10:16data in here.
10:18And dynamic data is the region that
10:21enlarges or shrinks during runtime. So,
10:25if we are, for example, generating some
10:27data,
10:29we are putting this data to the dynamic
10:30data section while running the code.
10:34For example, in here,
10:36if there are, for example, 32-bit
10:38addressing regions, our memory is, for
10:41example, 2 to the 32, it is 4 GB. Such a
10:442 to the 30 is 1 means 1 GB.
10:48Uh 2 to 2 4, so it's 4 GB.
10:54So, how computers work?
10:57Now, assume that I put my program to
10:59this text section, and here is my text
11:02section.
11:03And how this program loaded into the
11:07memory is
11:09run by the processor.
11:12So, normally, we have a counter, and
11:15this counter is named as program
11:17counter.
11:19And this program counter counts the
11:20memory location that
11:22uh
11:23that points to do
11:26currently run instruction.
11:29For example, program counter points to
11:32this location and this location as a
11:34data.
11:36And this data is an instruction.
11:39So, PC
11:40points to the currently executed
11:42instruction. Points to here. We have
11:44also hard disk, but generally
11:47we run programs from memory because
11:49memory is much faster than the hard
11:51disk. We will see in the uh maybe after
11:54four, five weeks we will compare them,
11:57but memory is around
11:59to
12:0020, 30 nanosecond. Hard disk is around
12:02maybe microsecond
12:04microsecond microsecond.
12:07So, for this reason we are putting the
12:09instructions to the memory and running
12:11it from there.
12:13So, PC points to the
12:16currently run running instruction and at
12:20each time
12:21we get the instruction from the PC, send
12:24it to the processor, and processor does
12:27some computation,
12:28and after this computation
12:31we are switching to the next PC.
12:33Uh maybe I can show you our slides.
12:37So, for example, we are now pointing
12:38this PC and this instructions runs,
12:42and we are switching to the next PC. And
12:44next PC has another instruction. We are
12:47running it, switching to next PC. We are
12:49increasing the PC by one one by one.
12:52Uh by the way, if you have for example
12:54multi-issue processor, if your processor
12:56can run maybe four instructions at a
12:58time,
13:00at that point you will have to increase
13:02your PC four instructions at a time.
13:04So, instead of for example, switching
13:06from here, you need
13:09to here, you need just jump to here.
13:12Just read four instructions at a time,
13:13but we will see this concept later.
13:17So, program counter keeps track of the
13:19current instruction, and each time
13:21processor gets the instruction from here
13:24and does some computation. And now we
13:27will see how it is doing to computation.
13:33So, RISC-V is a modular instruction set
13:36architecture. It has many extensions
13:39depending on the domain.
13:41Normally, RISC-V has a base instruction
13:44set which is named as I.
13:47This is base integer set. It has around
13:4940 instructions in here.
13:51But,
13:53of course, this 40 instruction is not
13:54enough. For example, if you want to do
13:56multiplication,
13:57you need to have M extension.
14:01If you want to do some floating-point
14:03operations, for example, you you need to
14:05have FD
14:07FD extensions. Q is also possible. F
14:11means 32-bit
14:13floating-point. D means 64-bit. Q means
14:16128-bit.
14:19V is vector operations for vector
14:21operations. For example, if you want to
14:23add, for example, you have a
14:2616
14:27uh
14:2816 vectors. And if you want to add them
14:33as parallel, V is used for the that
14:36purpose.
14:37So, by using the V operation, you can do
14:40vector
14:41executions.
14:43There are decimal floating-point, bit
14:45bit manipulation, atomic operations.
14:47Atomic is more related to operating
14:49system to run operating system. There is
14:51a compressed one. Uh
14:53GT uh
14:56and
14:57all these
14:59ex
15:00extensions are actually for the to run
15:03to do some operations.
15:05And also, there are some more
15:08extensions.
15:09Actually, they are named as
15:11specification.
15:12Like machine level, supervisor level,
15:15hypervisor.
15:16This is to for to run operating system.
15:22Normally, we have machine level, but if
15:24you want to run an operating system by
15:27in on the RISC-V processors processor
15:30that you built, you need to add also
15:32supervisor level uh
15:34user level. There is also user.
15:37Uh but in this class, you will not see
15:40these concepts much. We will see only a
15:42little bit,
15:43but this is of course maybe in more
15:46advanced class.
15:47If you want to check if you want to
15:49inspect the RISC-V extensions, you can
15:51visit this website docs.riscv.org.
15:55And this is a very nice website. In
15:58here, there are profiles, platform,
15:59system architecture. Even yeah, apart
16:01from the for example, when you visit
16:03this website
16:05even apart from the processor rather
16:08than the rather than the processor, it
16:10also has some extensions
16:13regarding the peripherals. For example,
16:17it If you want to use a fast very fast
16:20For example, if you want to connect very
16:22fast uh
16:23device to your RISC-V processors, it has
16:26also some standards
16:27uh showing how to do it.
16:32Even it has a for example server
16:34specifications in here. If you want to
16:36build a server processors by using
16:38RISC-V,
16:39there are some specific ex- standards in
16:42here you can follow.
16:44But mainly
16:46there are two
16:49uh two standards in here. One of them is
16:51unprivileged. Unprivileged this part
16:54just the instructions that are they are
16:56doing computation.
16:58And privileged
17:00is this part to run operating system.
17:03This privileged part is to run operating
17:05system, and unprivileged one is to do
17:09computations.
17:13Is it clear?
17:16So, RISC-V has more than
17:18thousands of instructions in various
17:20extensions, and we cannot teach them in
17:24a
17:25in a one semester. It is impossible.
17:28But,
17:29in this class, we will see the some
17:31concepts, and these concepts will be
17:33useful to build a
17:35high-performance out of processors, and
17:39in order to do this processor, we will
17:41only see a
17:43some limited extensions, like C
17:46extension, I extension, M extension,
17:48maybe.
17:49Uh but, after learning these concepts,
17:51you can just read the
17:53RISC-V standard and add these
17:56instructions also. Even you can add the
17:59user level, supervisor level extensions
18:02to run operating system. The important
18:04one is the concepts, how to build a
18:06high-performance processor, and after
18:08learning it, uh you can just read the
18:12specification for these instructions,
18:14and you can apply the same concepts to
18:16the processors you you develop.
18:22So, in this class, we we we are going to
18:24focus maybe I extension, M extension,
18:27and C extension, and for the rest, you
18:30can
18:31if you want to enlarge to
18:34more work, you can read and apply them
18:37to your processor.
18:41So, once you have learned one
18:43architecture, it is easier to learn the
18:45others. For example, in this class, you
18:47will see the concepts for to build a
18:50RISC-V processors,
18:52but by using these principles that you
18:55learned, you can easily implement it for
18:57the ARM processors also, because the
18:59concepts are same. The
19:01The working principles of the processors
19:04are always same,
19:06whether it is Intel, ARM, or RISC-V.
19:10So, why RISC-V is important? RISC-V
19:12started around 2017. Uh
19:17they are
19:19actually
19:20they are
19:22improving their processor architecture
19:24extensions and the
19:26processor architectures day by day.
19:29Uh there are lots of companies are
19:30trying to build high performance RISC-V
19:32cores
19:33uh from basic ones to even server grade
19:37processors.
19:39So
19:40Actually, it started around 2010,
19:42but in 2017
19:45around, they found the RISC-V
19:47organization for standardization.
19:50So when you look at here, the first
19:52RISC-V processors
19:54were the basic microcontrollers.
19:58Uh like the microcontroller inside this,
20:01for example, projection controller,
20:04remote controller.
20:05And day by day, they start to build more
20:08complex processor. For example, this
20:10T-Head CPU is a very complex processor
20:13that can run a mobile phone.
20:15And now they start to even build server
20:18processors.
20:20So
20:21for this reason, it is very good chance
20:24for
20:25especially for Turkey Turkey, uh since
20:28we have no national processors, we can
20:31get exploit RISC-V
20:33and then build our own national
20:35processors.
20:38By the way, even people are start to
20:40build
20:41uh GP GPU GPUs by using RISC-V. This is
20:45a work from Georgia Tech, Vortex. It is
20:48a
20:50They are building the GPU by using
20:52RISC-V instruction set architecture.
20:57So
20:59in here, let's start the
21:02RISC-V instruction set architecture.
21:05We can be familiar some some
21:08instructions.
21:12So, instructions are the commands in
21:14computer's language. Actually, they are
21:16the assembly language.
21:18They are two two types, by the way.
21:20Assembly is the human-readable format,
21:22like add, for example.
21:24When I say add, you can understand.
21:27Machine one is the computer-readable
21:29format. For example, add corresponds to
21:3110100, for example. Machine can
21:34understand this one. We are
21:35understanding this one. But, they are
21:37the same.
21:39Assembly is the human-readable format,
21:41just to convert it to
21:43machine, you are just changing this text
21:46to binary numbers.
21:49So, for example, in here I have a C
21:51code.
21:52It says that B plus C assigned to A.
21:54When I convert it when I compile this C
21:57code and convert it to a RISC-V assembly
21:59code, it is add A B C.
22:03This
22:05assembly code says that
22:08do addition of B and C and assign the
22:12result to A. It is just this this
22:14expression.
22:16So, this is the sub instruction.
22:19Subtract C from B and assign it to A.
22:22This this one.
22:24These are the first two instructions
22:26that we see in this class, add and sub
22:29RISC-V instructions.
22:33This is the assembly code. But,
22:34normally, these are converted to ones
22:37and zeros.
22:39And these ones and zeros runs on the
22:42processors that we will do develop.
22:45Yeah, add in here is the mnemonic,
22:47indicates the operation to be to be
22:49performed. B and C, the source operands
22:51in here,
22:53uh
22:54on which the operation is performed, and
22:56A is the destination operand, which is
22:58the result.
23:01So, in order to build two more complex
23:05functions, we are just
23:08combining these RISC-V instructions in a
23:12sequential manner. For example, in here
23:13I have a C code
23:15and when I compile this C code,
23:18I can no longer express it with a single
23:21assembly code. So, I am trying to do it
23:24in a two
23:26separate instruction
23:27run sequential. The first one is at B
23:30and C and assign is it to it T, assign
23:34it to T, and then second one,
23:36uh this is T, and second one do the
23:38subtraction for this part and assigns it
23:40to A.
23:43So, if you want to build FFT for
23:45example, more complex computation, the
23:48the same methodology is the same. We are
23:50just compiling the C code and this C
23:52code C code compiled into uh assembly
23:56codes and these assembly codes are run
23:59uh sequential.
24:02In here, the important concept is that
24:04these operand locations,
24:07so for example, I told you B and C, but
24:09from where these B and C comes from and
24:13where is the location of A also? Uh
24:16the operand location, it's the physical
24:18location of the information in computer
24:20where A, B, C comes from.
24:23Uh there are three operand location in a
24:27processor. One of them is the constants,
24:29also called immediate.
24:31It comes
24:33together with the instruction. Inside
24:35the instruction, we are coding the
24:37immediate. We will I will show.
24:39Or it can come from register or it can
24:42come from memory because previously I
24:44told you that memory has can also has
24:47data. This for example, dynamic data or
24:49global data. So, the the
24:53these data can come from there also.
24:55From memory. So, these are the three
24:57locations uh for the information.
25:02Constants, registers, and memory.
25:05So, the first one we can inspect the
25:07register.
25:08Uh registers are
25:11in here I showed the register.
25:14Registers
25:18These register file actually they are we
25:20are we call it as a register file.
25:22Register file is a storage inside the
25:25processor.
25:26And in this register file we are storing
25:29the
25:29uh some information in here. This is
25:33like a in you remember in the previous
25:35lecture I showed you a system verilog
25:38description
25:39uh for memory and this is a just a
25:42memory inside the processor, okay?
25:45And this is a
25:48location for storage
25:51inside near the inside the processor
25:53actually and RISC-V has 32 32-bit or
25:5764-bit registers.
26:02This uh actually this comes from RISC-V
26:05standard.
26:06Uh RISC-V says that if you want to build
26:08a RISC-V processors, you have to put
26:1132 registers and these register
26:15can be either 32-bit or 64-bit.
26:19Uh how we are defined these these
26:21deciding on 32 or 64?
26:24Uh we are deciding on
26:26based on the whether our processor is
26:2832-bit or 64-bit.
26:31If processor is 32-bit, then we are
26:34putting 32 32-bit registers. If
26:36processor is 64-bit, we are putting 32
26:3964-bit registers, okay?
26:42So, inside the processor we are building
26:45we have a register file.
26:48And this register file, this is a RISC-V
26:51processor.
26:52And this register file, for example,
26:54assume that
26:55it is 32-bit 32
26:5832
26:59* 32-bit register. So, it has a 32
27:02location from 0 to 31, and each of these
27:05locations are 32-bit. Okay?
27:08And these are the
27:10special names for these registers.
27:12Actually, they are the they are named as
27:14X0 until X31, but they have also some
27:18special names like zero, ra, sp, gp, tp.
27:23And in here, there are
27:25uh definitions, special purpose for
27:28these registers.
27:30Uh you can either use the name of the
27:33special name or
27:36the X and the register file number.
27:39Uh but generally, if you if you compile
27:42a C code, uh what you will see is this
27:45using name these names, special name,
27:47not the number.
27:50So, there are some registers in here.
27:52They are used for specific purposes. For
27:55example, X0,
27:57which is always zero.
27:59There are saved register, for example,
28:02S0 S11, between S0 and S11.
28:06Uh
28:08these these two and, for example, these
28:11these ones, for example. They are used
28:13to hold variables.
28:14Uh
28:15there are T0 and T6 registers.
28:18Where is it? Yeah, this part and this
28:21part, for example, T0 corresponds to X5.
28:25Uh they are used to hold intermediate
28:27values.
28:28Uh
28:30but
28:31generally, this meaning
28:33is not much uh
28:35yeah, we don't have to
28:36deal with this naming
28:38because this naming [clears throat] is
28:41uh from the software perspective of
28:44bill. But we are going to focus on is
28:47the actual register name. We don't
28:49Because this usage is related to
28:51software.
28:53Uh for this reason,
28:55this usage and we we don't deal with
28:58while designing the processors actually.
29:01We are for for us all register has the
29:04same meaning. So, for this reason we
29:07don't deal much attention to this usage.
29:09But, of course, as also since you are
29:11developing your own
29:13processors uh you can write software on
29:16it also for it. Uh so, you can you it's
29:20better to know also some the the usage.
29:27So,
29:29So, the register was the one of the
29:32places that the data can can come from.
29:35The other one is the immediate.
29:38Uh immediate available from instruction
29:41directly.
29:43So, how it is available? For example, in
29:46here
29:48I have a C code and C code says that
29:52add the A to six and assign it to B.
29:56And A is a minus number.
30:00When I compile this C code into a risk-5
30:03assembly code
30:05it puts another instruction.
30:08Add instruction still, but it says that
30:11add I. It is a add I.
30:13And this add I instruction says that
30:16add zero
30:18with minus uh
30:21372
30:23and assign it to S0. But, previously I
30:26saw my add instruction and this add
30:28instruction was saying that, for
30:30example, add
30:32X3 by X4 and then assign it to X2.
30:38In here
30:40we added a new instruction. It says add
30:43immediate. And this immediate, which is
30:46a data information, this immediate comes
30:49directly from instruction. Inside the
30:52instruction, this immediate will be
30:54encoded.
30:55And this is the immediate part. So,
30:57instead of adding two registers, for
31:00example, in the register one
31:02where data comes from,
31:04uh
31:05if you want to use register, for
31:06example,
31:08you are just doing such computation. For
31:11example, these are two registers. They
31:13are added, and then result is written
31:16to X2.
31:19In here, in this add immediate
31:21instruction, I have still two registers.
31:23One of them is the target.
31:25Other one is source.
31:27But this one is not another register.
31:30This one is the immediate. And this
31:32immediate is directly encoded inside the
31:34instruction.
31:38So,
31:40actually, this add immediate instruction
31:42directly corresponds to this assignment.
31:45In here, I am defining a variable. This
31:47is 32-bit variable. And this variable is
31:51get assigned this value.
31:53And how can I do it with RISC-V assembly
31:56code?
31:57I can just, in order to do an
31:59assignment, I can just add
32:03zero to this immediate value and assign
32:05it to to the register that I want to
32:08store this information.
32:11So, in here, from this point, we can see
32:14the
32:16usage usage of this zero register. This
32:19zero register is useful for such kind of
32:21assignments. Because in here, I told you
32:23that this X0 is always keeps the value
32:26of zero.
32:28So, why we are using this X0 register?
32:32Uh
32:33So, for example, in order to such kind
32:35of assignments, initializations, I can
32:38just use zero register and this zero
32:41register since this zero register has no
32:43effect
32:44whenever I do the S the addition with a
32:47immediate
32:49I can do the assignment to S0. So, this
32:52statement corresponds to this assembler
32:55instruction. What about this one? Uh
32:57this one still uses at immediate, but at
33:01that point I am doing the computation
33:03over A, so A was in the location of S0.
33:07So, I am adding six to this S0 and then
33:12assigning to the S1. So, S1 means B in
33:14here.
33:17So, for example, in here
33:19uh I used a
33:2112-bit signed signed constants immediate
33:24using addi add immediate operation.
33:29So, what about for example, I want to do
33:31an operation, but
33:33my immediate is more than 12 bits.
33:36Uh
33:37in this way, because RISC-V says, we
33:40will see it in detail. RISC-V says that
33:43if you want to do
33:44if you want to use add immediate command
33:48immediate field can be maximum 12 bits.
33:52It cannot be more than 12 bits.
33:54But what about for example, I want to do
33:56an assignment and it is more than 12
33:58bit, like for example, FFFF. For
34:01example, this is more than 12 bit. This
34:04is 16 bit for example. How can I do it?
34:07Uh
34:10I can do
34:11I can use more than one
34:14instruction in here.
34:16So,
34:19in here I'm introducing here another
34:20instruction,
34:22which is named as load upper immediate.
34:25And if my immediate is more than 12 bits
34:30uh Uh, in this case, I can use load
34:32upper immediate instruction. For
34:34example, I have a such an assignment.
34:36And in here, I want to assign this
34:40number to A. A is a
34:42register in
34:44in the in in the risk-five register
34:46file. This is 32-bit.
34:49So,
34:51this load upper immediate instruction
34:53puts an immediate in the upper 20 bits
34:57of destination register
34:59and zeros in lower
35:0112 bits. So, for example, I have a
35:03register in here. This is my register
35:05file.
35:06And I have a register X3 in here, for
35:08example.
35:10When I use this load upper immediate
35:12instruction, this load upper immediate
35:14instruction gets the 20-bit immediate.
35:17This is, for example, this this
35:19instruction, for example, load upper
35:20immediate S0, and this is the value.
35:2412-bit.
35:25It gets this value.
35:28For example, I assume that should I Here
35:30is S0.
35:31And
35:33when I run this load upper immediate
35:35instruction,
35:36this value becomes this 20-bit
35:41value.
35:43And it fills these
35:45lower 12 bit with zero.
35:49Okay? Now,
35:50I loaded this part of the
35:53variable, right?
35:55I loaded this part of the information.
35:58So, I loaded 20 bit of this information,
36:01but I have to also load this 12 bit.
36:05What can I use to load this 12 bit?
36:09How How can I How can I do it?
36:13I can just use add immediate, right? Add
36:15immediate instruction. So, for this
36:17remaining part,
36:19I can just
36:21add the value with this 12-bit value,
36:26which means that I am filling this the
36:28remaining part also, adding it and
36:31assigning it to over S0 again.
36:38Is it clear?
36:40So, until now which risk five
36:42instructions we see?
36:44Add,
36:45sub, add immediate,
36:48load upper immediate.
36:51There is a slight difference in here.
36:53Add immediate can get only 12-bit,
36:56maximum 12-bit
36:57immediate. Load up upper immediate can
37:00get 20-bit immediate. There is a
37:02difference between them.
37:04Uh you will see why this is so in the
37:07coming slides.
37:09Because you will will start to see also
37:11encodings of the instructions.
37:14And
37:15all these instructions are actually in
37:17memory. They are 32-bit.
37:21So,
37:22in this add immediate instruction for
37:24example, I have a target,
37:27I have a source register one,
37:30and immediate value. Since I have a
37:32target source register and also this
37:35instruction needs to has some
37:37information to show which operation it
37:39is
37:40doing.
37:41The for the the space left for the
37:44immediate is just 12-bit. But look at
37:47this load immediate load upper immediate
37:50instruction. This interaction has no
37:54source register field. It has just
37:56immediate.
37:57For this reason, in this instruction,
38:01within a 32-bit limited uh place, I can
38:05put 20-bit immediate. But we will we
38:08will see them in the
38:10coming presentations.
38:16So,
38:17where data comes from? First one, it
38:19comes from registers. But we will see
38:22how we are putting data to the registers
38:24at the end because when when you start a
38:26processor, registers are unknown. We
38:29didn't initialize it because this is
38:30just a
38:32flip-flops. We have to initialize them.
38:34We will see how we are going to put data
38:38to registers.
38:39Uh but data firstly comes from
38:42registers.
38:44Other source is immediate.
38:46And the third source
38:48memory.
38:50Where data comes from.
38:52Uh
38:53so
38:55the third place the data comes from is
38:58the memory.
39:00Because I told you that the RISC-V
39:02register file has 32 places. Each of
39:06them is 32-bit or either 64-bit. It
39:09depends on the processor that you build.
39:11Uh while designing the processor, you
39:13can either build your processor as
39:1532-bit or 64-bit. It's a actually a
39:20scale.
39:21Precision of the processor.
39:23Uh
39:25But this register file is small. So it
39:28is not enough to build
39:30very complex programs.
39:32Uh so actual source of the data
39:35is the memory.
39:38So we can store more data in memory.
39:40Memory is large but slow.
39:42Uh so memories commonly used variables
39:45kept in register. Uh yeah, commonly used
39:48variables kept in register
39:50uh because register is faster because it
39:52is inside the memory inside the
39:55processors.
39:56Uh but it is small. For the reason, if
39:59our program is working too much data, we
40:02have to put of course
40:04other data in memory and read from
40:06memory.
40:09So there are three sources for the data
40:11information, memory, register file, and
40:13immediates.
40:15Actually, they are they are sources also
40:18only memory. The data can come from only
40:21memory. Because immediate is an
40:23instruction, instruction comes from
40:25memory. And we will see that in order to
40:27load information to register, we will
40:30use load and store instructions. And
40:32these load and store instructions loads
40:34the information from memory. So, the
40:36actually only source is the memory.
40:41So,
40:43RISC-V also has some specifications on
40:46memory. RISC-V says that if you connect
40:49a
40:50memory to my processor, RISC-V
40:52processor, it assumes that the memory is
40:55byte addressable, not word addressable.
40:58Byte means 8-bit. So, you can access
41:02each 8-bit inside the memory, but you
41:04cannot access 4-bit. If you want to
41:06access 4-bit, you have to access as a
41:098-bit and get the 4-bit portion of it.
41:14So, each
41:15each data byte has a unique address. It
41:17means that it has a unique address.
41:20So, load store words or single bytes,
41:23load byte and store byte, these are the
41:25instructions, actually.
41:27So,
41:29this is, for example, my memory.
41:32And this is the address of the memory.
41:34And in this memory, I assume that here
41:36is 32-bit. 32-bit means that
41:39eight four bytes. In here, there are
41:42four bytes.
41:43So, for example, this is the this zeros
41:47stays in the address of zero. This one
41:49stays in the address of one.
41:51So, when you, for example, in this in
41:54this memory, each row has 32-bit.
41:58If you increase this, if you want to
42:00increase
42:01switch to the next row,
42:04you In this case, you have to increase
42:06your address by four. Because each row
42:08has four bytes. So, and this is byte
42:11addressable memory, you have to increase
42:13it
42:144 byte at a time.
42:17But still, of course, in if you want to
42:18access this this value, for example,
42:21this is address is 00002,
42:24for example.
42:32So, in RISC-V, in order to get data from
42:35memory, we will use the load
42:38operations. And in order to store data
42:40to memory, we will use the store
42:42operations.
42:44So,
42:45let's do this example.
42:47In here,
42:49I have the same code that I show you.
42:52But I didn't
42:56say that where this B and C comes from
42:59at the beginning.
43:02So,
43:03uh remember, at the beginning, I told
43:05you that after compiling our
43:08RISC-V program, we are loading it to the
43:10memory,
43:11and CPU reads these instructions from
43:14the memory and runs it.
43:15So, the initial place for a data is
43:18always memory.
43:21So, in this case, for example, assume
43:24that the
43:25this A and B and C are the locations in
43:28memory at the beginning.
43:30And assume that this A
43:34location of is A is
43:36uh
43:39Assume that Okay, these are the
43:41A location, B location, and C location.
43:44These are the locations in memory.
43:46This is A location. This is B location.
43:49This is this This is C location.
43:52So,
43:53when I compile this code,
43:58I know the address of A, B, and C.
44:02And
44:03in order to get the data stored in
44:06address of A and store it as zero.
44:10I I am using load word operation. Load
44:13word says that get to this address and
44:17load a word from there and then put it
44:20to S0.
44:22So, in here
44:23for example, when I run this code it
44:25goes to address of A
44:27and gets this X data and puts it to the
44:30S0 register file. This is the register
44:33Register file, by the way, is inside the
44:35processor.
44:36So, I am getting this X value and
44:38loading to the
44:40register file S0 location.
44:44This another load word, it says that
44:46gets the value of B uh get the address
44:49of B, get data Y data from there, for
44:51example, assume that there is a Y data
44:53in here and put it to S1.
44:55So, S0 X, S1 is Y.
44:59And do addition operation on S1 and S2
45:02and store the result to S1 and S2 and
45:06store the result S0.
45:10Yeah, in here, I think it should be S1
45:13and it should be S2.
45:15And
45:17result is stored in S0. So,
45:22S1 is X, S2 is Y and we are doing the
45:25addition and storing X + Y to S0
45:28location.
45:32If you want to do an immediate
45:34operation, it should be I.
45:37We are doing the add immediate and
45:41this is the same operation. So, in here,
45:43what I want to try to say is that
45:45at the beginning
45:47all these data are
45:49in memory, so in order to do operation,
45:52before doing the computation, I need to
45:55get this data from memory.
45:57And when I compile the program, I know
45:59the location of the data in memory.
46:02Maybe I can I can show you the example
46:04compiled program.
46:05In the compiled program
46:08everything all memory addresses are
46:10explicit. You can you can see all memory
46:13addresses.
46:15So, in order to do computation, first we
46:18need to get the data from memory.
46:21And in order to get data from memory, we
46:24are using the load word operations. Load
46:26word means this is word. Word means that
46:29get 32-bit
46:31So, what about for example, I want to
46:33store this value back?
46:35I want to use store word operation, for
46:36example. Assume that for example, I am
46:39storing it to the another location, C
46:41location.
46:43So,
46:44in this case
46:46for example, I want to store the result
46:48to C location. I need I want to I have
46:51to say S0, store S0 to the address of C.
46:56So, at that point
46:59we are putting this S0 to C location in
47:02memory. So, it is X plus Y. X plus Y is
47:05stored over here.
47:11Yes.
47:13Yeah, okay. Okay.
47:24So, the question was about the
47:27uh meaning of the word.
47:29In here, word means 32-bit.
47:32Uh double, if you for example, if you
47:35There are different kinds of load.
47:38One of them is load byte, load half,
47:41load word, and load double. Load double
47:43means that 64-bit loading. Load word
47:47means 32-bit loading. Load half means
47:49that
47:5116-bit, load byte means that 8-bit
47:53loading. And there are exact same store
47:56correspondence for them. Store bytes,
47:58store half, store word, and store
48:01double.
48:02For example, if you build that 32-bit
48:04processor,
48:06can you run load double instruction on
48:08it? No, no way, right? Because it is
48:1032-bit. Maximum The maximum data size is
48:1232-bit.
48:15So, and these are actual specific
48:19load operations.
48:25So, let's see. Now, we we we did a small
48:29introduction, brief introduction to
48:31RISC-V. So, we we can inspect the
48:35uh operations in more detail.
48:37Now, all these operations uh
48:41were from I extension.
48:43And now, I will show you the
48:46load
48:47memory operations, which is a part of I
48:50extension, also. I extension has memory
48:53operations, uh some arithmetic
48:55operations, add, sub, add immediate,
48:57load upper immediate, uh some more, and
49:01it has a fence instruction, but we will
49:03not see fence. Fence is a little bit
49:05more complex instruction.
49:07Uh
49:08we will see memory operations and more
49:11remaining arithmetic operations.
49:15So,
49:17in here, the most basic one is the load
49:19word. Load word is a load a word of data
49:21at memory address, for example. In here,
49:24for example,
49:27address is in terms of
49:29immediate, also.
49:31This is the address part. Load word says
49:33that load word register, register name,
49:38address.
49:39And this address actually
49:43consists of two parts, by the way. Uh
49:46not immediate. It has two parts.
49:49One of them is the immediate part.
49:52Other one is the register part.
49:54So, in here this is the register part of
49:57address. It says that zero register and
49:59immediate part of the address is eight.
50:02In order to resolve address, these two
50:05fields forms the address. How we are
50:08forming? It is very basic. We are just
50:10adding them.
50:11So, in here this instruction says that
50:15load this address to S3.
50:19Get to this address, access to this
50:21address, get
50:2332-bit data
50:25and put it to the S3 register.
50:28So, how we are building the address,
50:30deciding on the address? We are just
50:32adding this immediate.
50:34This is the immediate part to this
50:36register. Immediate
50:40plus register
50:42is the address in here.
50:45So,
50:47since this is zero register, zero
50:48register always keeps zero.
50:51Then, address is eight.
50:53So, I am going to address of eight in
50:55here. This is the address of eight.
50:58And this instruction says that read
51:0132 bits from this register. So, this is
51:04the 32-bit value that we read from this
51:07this address.
51:17So, these locations. So, for example,
51:18this is the data. By the way, this is
51:20address 0 1 2 3 4 5 6 7. This is
51:23address. This is the data. So, if I want
51:26to read a word from this address, I have
51:29to read
51:30this data. 2 4 8 2 E E 1 0.
51:36This is the value. So, what about load
51:38byte for example? If I say load byte S3
51:41and here is
51:45seven
51:46and here is zero for example. What What
51:48about this one? This is address seven.
51:50So, I need to go to address seven. So,
51:53address seven is
51:54uh
51:55here is zero, four.
51:57Uh address seven is here, right?
51:59Yes, see.
52:01Four, five, six, seven.
52:03So, this load byte
52:05is getting this data, because this is
52:08byte byte reading, we are just getting
52:10F2, one byte.
52:12And I am putting this one byte to this
52:14S3.
52:15But, S3 is 32-bit.
52:19I'm just loading
52:21this F2 to the first two
52:24byte first two first bytes.
52:27And for the rest, I am sign extending
52:30it.
52:31We will see this in the section. This is
52:33load byte. Load half,
52:34uh if you want to do load half, for
52:37example, load half
52:39six, for example, you are just getting
52:41these two together.
52:45Because half is
52:4616-bit.
52:51So, after this load this load word
52:53operation,
52:55we are just getting this value and
52:57putting into the register of S3.
53:00By the way, I'm saying S3, but S3
53:03corresponds to Let's Let's look. I I I I
53:06haven't
53:07I haven't didn't memorize it. No need to
53:09memorize it. But, S3 Let's check.
53:13S3 is
53:15X19, for example. I didn't know that. No
53:18problem. Yeah, no need to memorize it.
53:27So, load has different vari- variations.
53:29One of them is uh whether it is signed
53:32or not. Uh signed load sign extends to
53:35create 32-bit value to load into
53:37register. If it is
53:3964-bit processor, then it extends to
53:42create 64-bit value.
53:45It has also load half word and load byte
53:48variation. And for 64-bit processor, it
53:50has a load double variation also.
53:53Uh it has a two kind of uh in terms of
53:56sign. One of them is signed and other
53:58one is unsigned.
53:59Uh the for unsigned, it is it's zero
54:02extends.
54:03Uh
54:04so, it has also this is the signed
54:06versions. These are the signed versions.
54:09Uh load double, load
54:12uh word, load half, and load byte. They
54:15are signed versions. And if you add a
54:18unsigned, there is no load double and no
54:21load double unsigned. But if you add a
54:23unsigned, for example, load half
54:25unsigned, load byte unsigned,
54:28while getting a 8-bit value
54:32and
54:33putting it into the register, it zero
54:36extended.
54:38If it is signed, like for example, load
54:41half, it
54:43to a does sign extension. So, this is
54:46byte, for example, and this sign bit of
54:49the byte extended in here to keep the
54:51sign
54:52of the this value.
54:57So, store is the reverse operation. It
54:59stores the value in this register
55:03to this address. Addressing is the same.
55:05It has a register and immediate. And
55:08this immediate can be 12-bit, by the
55:10way.
55:11Uh I told before. So, in order to find
55:14the actual address, we are
55:17get we are
55:19adding the register to the
55:21to the immediate.
55:24So, for example, assume that T7 in here
55:28keeps this value AABBCCDD.
55:31If we run this operation store word is
55:35seven, we are just storing T7 to this
55:38memory address.
55:41So, what is this address? This address
55:43is 16 decimal actually. This is
55:45hexadecimal number. 10 hexadecimal is 16
55:48in decimal. So, we are just putting
55:51T7 into address 16. Address 16 is here.
55:55So, this is word store word. It means
55:58that 32-bit storing.
56:01So, we are putting this value, this 0 x
56:04a a b b c c d d value to here.
56:07So, this is the new value.
56:12So, we will see some arithmetic
56:15operations also.
56:19But, we can give a break
56:23and then continue.
56:29So, let's break from here.
56:49Okay.
56:52So, we will see
56:54more instructions from the I extension.
56:57The first ones are the logical
56:59instructions. These are basic operations
57:01and or XOR. And there are immediate
57:04versions of it also. And is actually
57:07useful for masking bits. It's just an
57:09operation, bitwise and operation. Or
57:11useful combining bit fields. It's
57:14bitwise or operation. XOR is bitwise or
57:18XOR operation. It is useful for
57:20inverting bits.
57:22Uh
57:23and now
57:25these are for example some values,
57:28source register values. Each of them are
57:3032-bit. And these are the results of
57:33this assembly operations. And operation,
57:35or operation, XOR operation, results of
57:37these operations. You can check them
57:38from the presentations.
57:42And there is a immediate version of
57:45these operations. This is the and or
57:47XOR. In here, the source operands are
57:49from registers. Two source operands are
57:51comes from the registers. And there is
57:53immediate version of these operations.
57:56It is
57:58ended with I. It means that and
58:00immediate.
58:01And in these I operations, one of the
58:04operand comes from the register, and
58:06other one comes from the immediate
58:08value. But this immediate value is
58:1012-bit.
58:12So, but this register is 32-bit. So, it
58:16means that we are doing an operation
58:19between 32-bit value and 12-bit value.
58:22But what about the remaining 20 bits?
58:25So, in order to find the 20-bit bits,
58:28we are always sign extending it. So, for
58:31example, this is our immediate value,
58:3332-bit uh 12-bit, sorry.
58:36And I want to do an operation with T3
58:38register.
58:39And this immediate value is sign
58:41extended. And this is the result, for
58:43example. This is the operations and
58:45immediate, or immediate, XOR immediate.
58:47And these are the results of these
58:48operations. But in here, the important
58:51point is that always we are sign
58:53extended the immediate field.
58:55Because we need to match it to 32-bit.
58:57We need to extend it to 32-bit.
59:00And this is sign extension. If, for
59:03example, this bit is zero, then sign
59:06extended puts fills it with zero. If
59:09this is one, sign extension fills it
59:12with one
59:13to
59:14keep the value of the value. This this
59:17this data.
59:20Sign of the to to to keep the
59:23to protect the sign of this data.
59:26Another kind of instructions, shift
59:29instructions,
59:30uh shift uh
59:33amount is lower five bits of a register.
59:36So, shift left logical, shift right
59:38logical, and shift right arithmetic
59:41operations.
59:45So,
59:47in here, there are two registers,
59:50and this
59:52second register corresponds to shift
59:54amount. It shows the shift amount.
59:57For example, in here, I have operations
1:00:00shift left logical,
1:00:01and this is the uh
1:00:03T1 value, this is T2 the value. Uh this
1:00:06is the
1:00:07operands, and T2 T0 is the result.
1:00:12So, in here,
1:00:14this is the value
1:00:16that is that will be shifted, and this
1:00:18is the shift amount. Shift amount,
1:00:21shamt.
1:00:22In respect spec, they say it as a shamt.
1:00:26It means a shift amount.
1:00:28But, in here, there is a
1:00:31important point in order to to shift a
1:00:3332-bit value,
1:00:36for example, this is also another 32-bit
1:00:38value
1:00:40that needs to be shifted.
1:00:42But, you can shift this value
1:00:46maximum 32 bits, right?
1:00:48You cannot shift after 32 bits.
1:00:51So, for this reason, we are only using
1:00:55the least significant five bits of the
1:00:57second register that shows the shift
1:00:59amount. Is it clear, right?
1:01:01So, otherwise, because if, for example,
1:01:04trying to sh- for example, say that we
1:01:06are getting six bits,
1:01:08if this value is, for example, 64 or 53,
1:01:12for example, doesn't matter. It always
1:01:14becomes zero. The value always becomes
1:01:16zero.
1:01:16So, for this reason, we are getting the
1:01:18lower fi- lower five bits of a register.
1:01:21This is for processor. If processor is
1:01:2364-bit, for example, we are getting the
1:01:26lower 6 bits of this register. But, in
1:01:29these examples, I'm
1:01:33only showing you always showing you the
1:01:3532-bit where I where I
1:01:3832-bit processor.
1:01:3932-bit variation of the processor.
1:01:43So, this is the value to be shifted, and
1:01:44this is the shift amount. And
1:01:48and we are storing the result in here.
1:01:51There are shift left logical, shift
1:01:53right logical, and shift right
1:01:54arithmetic operations. There are also
1:01:57immediate
1:01:58variation for it. Immediate is always
1:02:02ends with I letter.
1:02:04Uh
1:02:04so, shift left logical immediate, for
1:02:06example. And in here, second operands
1:02:08come from the immediate. And this
1:02:11immediate value is
1:02:13still turn 12-bit. Uh but, of course, we
1:02:16are getting Yeah, this
1:02:19We are getting still the
1:02:21between 0 to 31. Still
1:02:24uh
1:02:25Yeah, this cannot be, for example, more
1:02:28than In here, shift amount cannot be
1:02:30more than 32 still.
1:02:33We are just only using the
1:02:355 bits of it.
1:02:40So, set less than instruction. This
1:02:42instruction compares two value and sets
1:02:46the destination register as one or zero
1:02:49depending on the result. There are
1:02:51different variations. Uh actually, it
1:02:53compares two two registers two registers
1:02:58and then sets the result
1:03:01depending on whether it is set less than
1:03:04or not.
1:03:06There are immediate versions and
1:03:08unsigned comparison versions. Uh so, in
1:03:11here, the important point I also
1:03:13mentioned previously is 5 always sign
1:03:15extends the immediate. Even for shift
1:03:17less than immediate unsigned version,
1:03:20this one.
1:03:22So, here
1:03:23there is an example in here. There is S1
1:03:25and S2 registers keeping these values.
1:03:29And for example, in shift less than
1:03:30operation
1:03:32if I compare the S1 and S2
1:03:34uh this register just compares S1 and
1:03:37S2. If S1 is less than S2, it assigns T0
1:03:41as one.
1:03:43So, in here set less than comparison
1:03:46compares these two values, but since
1:03:49this value is negative, because this is
1:03:52eight. Eight means that 100. So, this
1:03:55most significant bit is one. So, this is
1:03:57a minus value, this minus value. And S2
1:04:01is
1:04:02positive number
1:04:03then
1:04:04it is correct. S1 is less than S2. So,
1:04:07T0 becomes one.
1:04:09What what about the unsigned version of
1:04:11it? In unsigned we are not representing
1:04:15it as a
1:04:16evaluating it as a signed value. It is
1:04:19unsigned. So, when you compare it as an
1:04:21unsigned, then
1:04:23S1 is greater than S2. So,
1:04:26this comparison is wrong. Uh so,
1:04:29T1 becomes zero.
1:04:31And this is the immediate version of it.
1:04:33And immediate version
1:04:35in the immediate field we are putting a
1:04:3712-bit number in here and comparing this
1:04:4012-bit number with
1:04:41the other register and resulting the
1:04:43result to a T2.
1:04:45This is the immediate version of it.
1:04:48Yes.
1:04:50>> Slide 12, what's the difference between
1:04:51arithmetic shift and logical shift?
1:04:57>> Yes.
1:04:59Okay, in here I Yeah, I forgot it.
1:05:03Yes.
1:05:05So, for example, this one says shift
1:05:07left logical immediate.
1:05:12Shift left shift Yeah, in here yes,
1:05:14there is arithmetic also.
1:05:17So, in here
1:05:19if you are logically shifting it,
1:05:22you are filling it with zero in here,
1:05:24okay?
1:05:27Because while shifting,
1:05:30you are filling it with zero.
1:05:32But, in shift right arithmetic,
1:05:34actually,
1:05:35while shifting it,
1:05:37for example, in shift right Shift right
1:05:40means that this location we are writing
1:05:42through this location.
1:05:44Uh
1:05:45By the way, this is a
1:05:47uh
1:05:49respective, actually, symbols for the
1:05:51shifting.
1:05:52In shift right arithmetic,
1:05:57this is all There is only, by the way,
1:05:58there is only a right version of this
1:06:00shift right arithmetic. For the logical
1:06:02one, there is left and right version of
1:06:05it.
1:06:06In shift right arithmetic, while
1:06:08shifting it, you are keeping the value
1:06:10sign value in here.
1:06:12Because otherwise, you you while
1:06:15shifting, for example, logically, you
1:06:17are adding zero.
1:06:18Okay? You are adding zero while shifting
1:06:22right or left.
1:06:23For example, if you are shifting through
1:06:25left, you are adding zero from here.
1:06:28While shifting logically from
1:06:31right, you are adding zero from here.
1:06:33But, in arithmetic one,
1:06:35still same, you are keeping the value of
1:06:37the register. So, you are just
1:06:39replicating for example, while shifting,
1:06:42assume that this is the value.
1:06:44While shifting this value
1:06:46by one bit, right? You are just making
1:06:49it as a 1
1:06:520 1
1:06:531 1 0 1.
1:06:55And you are just removing this one,
1:06:56shifting it this one, and just keeping
1:06:59this value. Assume that this is 32-bit
1:07:01value.
1:07:02This is the most significant bit. This
1:07:04is the difference.
1:07:07>> I can do it with
1:07:09logical shift. I can keep the value with
1:07:11shift already.
1:07:17Okay.
1:07:20But after shifting
1:07:22lots of times,
1:07:24for example, assume that it is a maximum
1:07:26negative value. If you shift left one
1:07:28more time,
1:07:30then there is no point to make it two
1:07:32times because you cannot keep this value
1:07:34already. There is There is not enough
1:07:35register to keep the maximum, for
1:07:38example, it maximum minimum one,
1:07:41minus two times 32, right?
1:07:44And if you shift it
1:07:46uh left by one bit,
1:07:49we can already we cannot keep the minus
1:07:52two to the power of 33. Or this is a no
1:07:55point for it. So, there is no version.
1:07:57But for the other one also, I can do it
1:07:59with logical shift. I can keep the value
1:08:02with logical shift already.
1:08:08And there are multiplication and
1:08:09division instructions
1:09:01>> And there are multiplication and
1:09:03division instructions. They're not I
1:09:06extension. This is the M extension of
1:09:08RISC-V.
1:09:10So,
1:09:12if the processor is 32-bit, if you want
1:09:14to multiply two 32-bit numbers, the
1:09:17result is 64-bit.
1:09:19It is not like addition.
1:09:22So, in here,
1:09:24if you multiply these two two 32-bit
1:09:27numbers with mul operation, this is a
1:09:29RISC-V operation,
1:09:31and assign it at the 32-bit value, this
1:09:34register always keeps the lower 32-bit
1:09:37result.
1:09:39Not the higher one.
1:09:41So, if there is an overflow, and if you
1:09:44suspect that the the result has
1:09:47overflow, then you need to also run the
1:09:49mulh function. This gets the
1:09:52highest bits highest 32-bits of the
1:09:55upper 32-bits of the bits of the result.
1:09:59So, the
1:10:00result is 64-bit, and lower 32-bit,
1:10:04it is computed by mul operation, and
1:10:07upper 32-bit, it's computed by mulh
1:10:10operation.
1:10:11By the way, this is valid for add. Also,
1:10:13if you add two 32-bit numbers, and the
1:10:16result is 33-bit, but RISC-V
1:10:19doesn't care it. It assumes it is
1:10:2132-bit. If you suspect that there is an
1:10:24overflow, you have to check it yourself.
1:10:27But for multiplication, there are two
1:10:28different operations
1:10:31to access the each 32-bit chunk.
1:10:35So, in here, there is an example. I'm
1:10:37just skipping.
1:10:38So, multiplication has two variations,
1:10:42unsigned and signed.
1:10:43And
1:10:45uh
1:10:45so, in for example,
1:10:48signed version is multiplication h. This
1:10:51is to get the upper 32-bit.
1:10:54In order to get the upper 32-bit as for
1:10:57example, as a result of
1:10:59uh
1:11:01let's say from here. For example, if you
1:11:04want to get
1:11:05uh
1:11:07the result
1:11:08and assume that both operands are
1:11:10unsigned, you need to use multiplication
1:11:13H unsigned.
1:11:14So, it is like doing the multiplication
1:11:16as unsigned.
1:11:18And if you assume that the first operand
1:11:21is signed and second is unsigned, you
1:11:24have to use multiplication mul H S U.
1:11:27One of them is signed, other one is
1:11:29unsigned.
1:11:30There are different variation of these
1:11:31multiplication operations.
1:11:35So, about least significant bits are
1:11:37same. You can always access it with mul
1:11:40operation. The least significant 32-bit
1:11:43is same. Whether it is signed, unsigned,
1:11:46or one of them is signed, other one is
1:11:47unsigned.
1:11:51But, why there is, for example, such an
1:11:53operation like mul H unsigned signed?
1:11:57For example, there is no such operation.
1:11:59Why?
1:12:00There is no need because instead of
1:12:03writing it as a
1:12:05X 2 X 3
1:12:08if this is in this way, I can just
1:12:10change the register locations. Compile
1:12:12can do it it. So, if compile can do it,
1:12:16RISC-V does not put any instruction for
1:12:18it.
1:12:19There is no need to keep space in the
1:12:20hardware because compile if can compile
1:12:23can do it, then compile it is better to
1:12:25to assign it to compiler.
1:12:31So, there is division remainder
1:12:32instructions uh div rem
1:12:35and there are unsigned versions of it.
1:12:38This is the same. We have two registers
1:12:41and we are doing two corresponding
1:12:43operations on them.
1:12:47These are the instructions from I N M X
1:12:51extensions.
1:12:52And in I extensions there are some more
1:12:56instructions. These are very important
1:12:58instructions. They are named as branch
1:13:00and jump instructions.
1:13:02While running a code
1:13:05sometimes we are coming to a decision
1:13:07point. For example, we are
1:13:09using if for example and checking a
1:13:12value of a variable saying that if A is
1:13:15one or not.
1:13:17So, there are types of branches
1:13:20conditional and unconditional.
1:13:22Conditional branches are compares like
1:13:24if for example, we are comparing two
1:13:25values whether it is equal, not equal,
1:13:27less than or greater than greater than
1:13:29equal. These are all risk five
1:13:31instructions to do this conditional
1:13:34comparisons.
1:13:36And there are unconditional versions
1:13:38like jump, jump register, jump and link
1:13:41and jump and link register. We will see
1:13:43all these operations in detail.
1:13:46So, in here the point is is that for
1:13:49example, you have a function for
1:13:51example.
1:13:54And
1:13:56assume that in this function I have a if
1:14:00equality check. I am checking whether if
1:14:02A is equal to three and
1:14:05in here in main
1:14:08you are calling this function function.
1:14:11You are calling it.
1:14:14For example, assume that our program
1:14:16start to work from main and start
1:14:19running.
1:14:20And in this location, in order to jump
1:14:23to this function
1:14:25this is a jump instruction because PC is
1:14:27going going going increasing linearly,
1:14:30but at that point it says that we need
1:14:33to jump to another location in the in
1:14:35the program. So, in order to jump this
1:14:39function location, we are using
1:14:41unconditional jumps.
1:14:45So, at that point we are using
1:14:47unconditional jumps to for example while
1:14:50running the program
1:14:52we are running it one by one.
1:14:54We want to assume jump for example
1:14:56somewhere else inside the programs.
1:14:59It is because programs are not linear.
1:15:01It It has decision points.
1:15:03So, in order to this kind of direct
1:15:06jumps without any condition, we are
1:15:08using jumps.
1:15:09And if there is a condition for example
1:15:12in for this if inside this function
1:15:15for example in here I am doing a
1:15:18comparison and if this comparison is
1:15:20okay
1:15:22true, then I am continuing, but if not
1:15:26I am going to another part of the
1:15:28program. So, while in here
1:15:30if this comparison is not correct, I am
1:15:33jumping to else.
1:15:34So, for this kind of jumps, I am using
1:15:37conditional ones because in here there
1:15:39is a condition. So, depending on this
1:15:41condition, I am jumping or not jumping.
1:15:45So, these are the two types of branches.
1:15:47One of them is conditional and these one
1:15:49of them is unconditional. These are the
1:15:51conditional respect instructions and
1:15:53these are the unconditional respect
1:15:55instructions. And in here I put an
1:15:57example, yes. If
1:16:02So
1:16:03in order to
1:16:05know the location where we are jumping
1:16:08uh
1:16:09compilers puts labels. And label
1:16:12indicates where to jump. Actually, label
1:16:14is a just memory location. And we are
1:16:16jumping this label, it means that we are
1:16:18jumping this location.
1:16:20So, it is represented in jump as
1:16:22immediate offset.
1:16:24So, it is immediate for example number
1:16:26of bytes past jump instruction.
1:16:29For example in here
1:16:31this is main code. Main code at that
1:16:34point says that jal simple. Jal means
1:16:36jump and link.
1:16:38Uh I will show link part, but jump means
1:16:40that jump to simple. So, whenever I
1:16:45come to this instruction,
1:16:48this add is no longer run.
1:16:51We are just jumping to this simple
1:16:53point. Just jumping to here and continue
1:16:56to continue to run from here.
1:17:01So,
1:17:02and this simple is a by the way
1:17:05a
1:17:06label. This is label. And this label is
1:17:10used to compute Actually, this label is
1:17:12a
1:17:14hexadecimal binary number actually. This
1:17:15is just a
1:17:17binary number.
1:17:18And we are using this label
1:17:21to compute the address that we are
1:17:23jumping to.
1:17:26So, for example, in here this jump jump
1:17:29simple, actually it is this instruction.
1:17:33JAL
1:17:35RA. RA is a register.
1:17:38This is maybe X
1:17:40I don't know. X2, X3 maybe. And there is
1:17:44an immediate value in here.
1:17:46And what we are doing is that we are
1:17:48just adding this value to our PC may
1:17:53existing pro- for example, program
1:17:54counter is in here.
1:17:56In order to find this simple position,
1:18:00instead of switching to the next program
1:18:02counter, I am changing my program
1:18:04counter as program counter plus this
1:18:06value. 0x21c
1:18:08for example, and jumping to here.
1:18:11This is how we are jumping.
1:18:15So, in here for example, this if this is
1:18:19this PC in here is assumed 300
1:18:22and this simple is placed in 15c,
1:18:27so this immediate field, the simple
1:18:30value of simple is 0x the minus of them
1:18:330x21c.
1:18:36Who is doing these computations? We
1:18:38don't We are not doing compiler is doing
1:18:40these computations. Compiler is placing
1:18:43if you compile some code, for example,
1:18:46and assume that this code has functions
1:18:49inside.
1:18:50Even
1:18:51for example, you are writing a code and
1:18:53running for example a printf function,
1:18:55but you are not writing printf function.
1:18:57Printf function belongs to the operating
1:18:59system. It is an operating system
1:19:01function.
1:19:02So, while running this operating system
1:19:04function,
1:19:06all addresses are
1:19:08decided by the compiler. We don't deal
1:19:10with them.
1:19:12For what should we do is that just
1:19:15implement jal function correctly,
1:19:18and whenever we saw this immediate
1:19:20field, we need to just add the PC to it
1:19:23and jump to this location.
1:19:25But we don't As hardware designers, we
1:19:27don't care
1:19:28the
1:19:30compilation steps. We don't know the
1:19:33where is the location of this function.
1:19:40So, in RISC-V, there are memory
1:19:42addressing modes,
1:19:44two memory addressing methods to access
1:19:46the operands. One of them is base
1:19:47addressing. Base addressing is used load
1:19:49and stores. We saw it already.
1:19:51So, address of the operand is decided by
1:19:54base address plus immediate. So, in
1:19:57here,
1:19:58I have a register
1:20:01and
1:20:0372.
1:20:04So, it is base address and immediate.
1:20:06Base address is the value stored in
1:20:08register. It means that this base
1:20:11address value stored in register, stored
1:20:14in register.
1:20:16And
1:20:1772 is the immediate. So, we are just for
1:20:20example, in order to do this load
1:20:21operation, we are adding them, and it's
1:20:24same for the store also. In here,
1:20:27I am doing addition, but this is signed
1:20:28value. So, it is like subtraction, but
1:20:31I'm still doing the addition.
1:20:35The other one is the PC relative
1:20:37addressing.
1:20:39As I
1:20:40briefly mentioned, just mentioned, so
1:20:42branches and jumps use this method.
1:20:46So, for example, in here I have
1:20:48instructions
1:20:50and assume that, for example, I start to
1:20:53run these instructions.
1:20:55I run this at I executed this sub and
1:20:58come to this point and in here I have a
1:21:00branch not equal instruction. What
1:21:02branch not equal is doing? It compares
1:21:05S8 and S9 registers and if they are not
1:21:09equal,
1:21:11it is jumping to
1:21:13the location
1:21:14uh this L1 location.
1:21:17To this location, to this L1 location.
1:21:21How we are computing the value of this
1:21:23L1 location? This is the assembly code,
1:21:25by the way. This is the assembly code.
1:21:27How we are finding the location of L1
1:21:29L1
1:21:30location A1 L1 label, this is label.
1:21:34How we are finding the value? It is
1:21:36actually 0 X 3 5 4.
1:21:40But from this point, I am jumping to
1:21:42here, jumping to this value. So, in here
1:21:46my label is
1:21:48uh the difference between them because
1:21:50it what when I was in here, I am
1:21:53jumping to here. So, the difference is
1:21:55between
1:21:56this value and this value. So, it is
1:21:59this one.
1:22:00So,
1:22:01whenever my PC is EB0,
1:22:05I am just adding this value to the PC
1:22:07and getting this value, which is the
1:22:09location of L1.
1:22:14So, in bra- branch
1:22:17branch not if not equal operation,
1:22:20I have to encode
1:22:22this difference value so that when I run
1:22:25this
1:22:26in- instruction, I need to add to it to
1:22:29the PC. How should I encode it? It is
1:22:32like
1:22:3312-bit immediate still.
1:22:36This is 12-bit immediate.
1:22:40So I'm encoding it as a 12-bit
1:22:42immediate.
1:22:44So it's also data comes from the
1:22:45instruction also. It's a kind of data.
1:23:00So okay.
1:23:02Let's skip this part. Don't worry. I
1:23:05will show it later.
1:23:06Because this is not the one that I saw
1:23:09shown earlier.
1:23:11So for branch types, there are signed
1:23:13and unsigned versions.
1:23:15Branch less than, branch greater equal.
1:23:18Branch less than unsigned and branch
1:23:20greater equal unsigned. This is this
1:23:23unsigned versions does the comparison as
1:23:25unsigned.
1:23:28Like the set less than operation.
1:23:30We did similar one in in set less than.
1:23:33So in here we have an example for branch
1:23:35equal instruction.
1:23:37Uh
1:23:38I'm now start to run this program.
1:23:41And when I come to this point, there is
1:23:43a branch operation.
1:23:44So PC increasing linearly. Okay?
1:23:50So when I come to this location, mine
1:23:53this PC I assume that in here I have my
1:23:56PC value. I'm comparing S0 and S1. And
1:24:00if they are equal, I am jumping to the
1:24:02target. And target is in here.
1:24:04So what about in here? We can run this
1:24:08program and see the actual results of S0
1:24:10and S1. So S0 is four, S1 is one.
1:24:14And then in here, shift less immediate
1:24:17shift left logical immediate
1:24:19instruction, should this shift left
1:24:22logical immediate shifts S1 two
1:24:25times. So, S1 becomes four.
1:24:28So, S0 was four. S1 was initially one,
1:24:30but after shifting, it became four.
1:24:33And when I compare these two values,
1:24:35four equal to four, that's true. We need
1:24:38to jump to target. So, these two
1:24:40instructions are not executed. So, I'm
1:24:43jumping to target.
1:24:44Uh so, target is my label in here, the
1:24:46location that I am jumping to.
1:24:49So, and continue this PC jumps to
1:24:52target, and I continue from this
1:24:54location.
1:24:56So, this location adds S1 to S0. So,
1:24:59it's 4 + 4 8.
1:25:02So, as I told you before, label indicate
1:25:05the instruction location. They can't be
1:25:07reserved words and must be followed by a
1:25:09comma in assembly code.
1:25:12Maybe I can show you more complex
1:25:14assembly examples in the next next
1:25:16lecture.
1:25:19So, in here also another operation,
1:25:21branch not taken. Assume that this
1:25:23branch the same
1:25:25instructions, but I changed this branch
1:25:28equal to branch not equal. So, in this
1:25:30case, when PC comes to here, I'm doing
1:25:33the comparison. Since they are equal,
1:25:36I'm continue I continue.
1:25:38I'm running add instruction, sub
1:25:40instruction. I continue. I'm not
1:25:42jumping.
1:25:43By the way,
1:25:46in in here, if I'm not jumping,
1:25:50the program continues
1:25:52here.
1:25:53And even after sub, if there is an add
1:25:56instruction, it runs it also because it
1:25:59continues.
1:26:01If there is no jump or branch, it just
1:26:03continues.
1:26:05So, it also runs this add. It continues
1:26:07in this direction. If there is a jump in
1:26:10here, it jumps to here, does not run
1:26:12these two instructions, but if there is
1:26:15a
1:26:16uh
1:26:18if there is a there is
1:26:20if this condition is not true then it
1:26:22continues to run.
1:26:25So what about jump?
1:26:27Jump is direct jump without checking any
1:26:29value. When you see a jump instruction
1:26:31you have to jump. No no condition.
1:26:35RISC-V has two types of conditional
1:26:37jumps. One of them is jump and link.
1:26:40So in jump and link operation
1:26:43I am I have a immediate in an in order
1:26:46to find the location to where I am
1:26:49jumping to I am adding it to the PC.
1:26:53But at the same time while jumping
1:26:56I am keeping the
1:26:59old PC value plus four to a register.
1:27:04This is very useful instruction. I will
1:27:06show why it is very useful. So in this
1:27:09jump and link operation link part link
1:27:11part means that storing the
1:27:15the storing the address.
1:27:19For example in jump and link operation
1:27:21in here I I have a for example jump and
1:27:24link
1:27:25uh
1:27:27going to somewhere else in here in okay
1:27:29in
1:27:31Let's see an example. You have no
1:27:33example. Okay while jumping to here for
1:27:36example in this position I assume that
1:27:39this is jump instructions. While jumping
1:27:41to here to this target
1:27:44I am saving the
1:27:46this PC plus four to a register.
1:27:51Assume that my PC is here.
1:27:54Next PC is PC plus four. Why? Because in
1:27:58in RISC-V each instruction 32-bit value
1:28:00and 32-bit value means that four byte.
1:28:03So while switching the instructions I am
1:28:05increasing by PC by four.
1:28:08So while jumping
1:28:11I am also storing the old PC plus four
1:28:15value to a register. Why I am storing
1:28:18it?
1:28:18Because
1:28:20assume that I am for example, I have a
1:28:22main function in here. And in main
1:28:25function, I am calling a function.
1:28:29And this function runs. And in this
1:28:32function, there is a return. Right? In C
1:28:34program for example. This main works. We
1:28:37are calling this function. This file
1:28:40This function switches to this this
1:28:42location.
1:28:43It jumps with jump and link operation.
1:28:47Why? Because after this function runs,
1:28:52while returning,
1:28:54we are saving while calling this
1:28:56function, we are saving the location
1:28:58that that we will return later to this
1:29:01location. So So while doing return, we
1:29:04can just return to value of this RD.
1:29:07Because this is our return address. The
1:29:09functions are
1:29:11works in this way.
1:29:13Is clear?
1:29:15We can repeat in Turkish if you want.
1:29:21Okay.
1:29:22So jump and link,
1:29:25it saves the return location to a
1:29:28register and then jumps. And in this
1:29:30location, we know the address of the
1:29:32return location because always functions
1:29:34returns.
1:29:36And
1:29:37this is jump and link operation. And
1:29:39there is also a jump and link register
1:29:41operation. In jump and link
1:29:44register operation, this is a register
1:29:46version of it.
1:29:49In order to find the new PC, normally in
1:29:52jump and link operation, we are adding
1:29:55PC to immediate and finding the new PC.
1:29:58In jump and link register
1:30:00operation, in order to find the new PC,
1:30:04I am adding the register with the sign
1:30:06extended immediate. and then finding the
1:30:08new PC.
1:30:10This is different. So, instead of using
1:30:12PC in here, I am using a register, a
1:30:1532-bit register.
1:30:17So, in here, there is a RISC-V assembly
1:30:19code.
1:30:22So, in jump instructions, limited
1:30:24immediate is limited 12 bits for jal.
1:30:28For example, in this jal
1:30:30for jal operation, 12 bits
1:30:33uh but if jump and link it is
1:30:3820 bits for jal and
1:30:4012 bits for jump and link register.
1:30:43So, this has this limits how far a
1:30:46program can jump.
1:30:48So, we cannot jump for example after 2
1:30:50to 12. For example, if we are using jump
1:30:53and link register.
1:30:55So, if you want to use
1:30:57jump further, for example, if you want
1:30:59to jump 2 to the 30, for example, there
1:31:02are special instructions. For example,
1:31:05this is a special instruction. It says
1:31:06that add upper immediate to PC.
1:31:10And this instruction actually
1:31:15gets this immediate, this is 20-bit
1:31:17value,
1:31:18and
1:31:19add upper immediate value, this 20-bit
1:31:23value, to the PC.
1:31:25So, you can jump further in this way.
1:31:27So, this instruction just do this one.
1:31:30PC plus immediate, this upper 20 bit,
1:31:34and zero, the first 12 bit zero, and we
1:31:37are
1:31:38adding them and writing to RD. And then,
1:31:41I can jump to this RD location by using
1:31:44this for example jump register
1:31:45instruction.
1:31:48Is this clear for the jump instructions?
1:31:56Yes.
1:31:57>> Okay.
1:32:02Okay.

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