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W1 Introduction EN — Transcript

by Hasan Erdem Yantır · 17,664 words · 3,095 segments · language en · Watch on YouTube

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0:03So, the class is about risk five
0:06architecture and processor design.
0:09And my name is Hassan Adam Yantar.
0:12I will introduce myself. This class is
0:14about
0:16a top-to-bottom understanding of a
0:18modern risk five processor system.
0:20So, in this class we will see how to
0:22design a very complex processor
0:25core, but not not the SOC itself. In
0:28here there is a die shot of Apple M4.
0:31And you you see there are different
0:33kinds of components in this die shot.
0:36You know, Apple Apple is the phone that
0:38you use
0:40commonly. And its processor consists of
0:43different components like GPUs, CPUs.
0:46And in this course we are going to focus
0:48on the CPU. And we will focus on the
0:50complex processor.
0:52Complex CPU.
0:55Not like the basic ones.
0:58And I will introduce it more in detail.
1:00I will mention about it in detail. My
1:03name is Hassan Adam Yantar. Actually,
1:04I'm a senior chief research researcher
1:07at the BİLGEM. And also at the same time
1:09I'm a part-time faculty at Istanbul
1:11Technical University. In the case of a
1:13need, you can contact me over this
1:15email.
1:18In here I mentioned that I mentioned
1:21about the term named risk five. And risk
1:24five is actually an instruction set
1:25architecture. And instruction set
1:27architecture defines how the CPU is
1:29controlled by the software.
1:32So, it's like a common language between
1:34the hardware and software. So, when you
1:37look at this picture,
1:39everything is consists of physics
1:41devices.
1:42And these devices combines and forms the
1:45digital circuits, analog circuits. And
1:47we have logic
1:49based on these digital circuits,
1:50microarchitecture, architecture, and
1:52application software through the
1:55top level application software.
1:58And when you look at any
2:01electronic component, for example, a
2:04processor, you are writing software on
2:06it, running software on it. Uh it's
2:09Okay, people are using it to write
2:11software, but under under the software,
2:14there are lots of different levels.
2:17Starting from physics until the
2:19architecture.
2:20And in here, you know, people they are
2:23writing the software, and also also
2:25there are also other people they are
2:27building the micro processor. And there
2:30should be a common language between
2:31them. Because the the one who is writing
2:34the software needs to know that
2:36how which software, how how should it
2:39write the software for this
2:41architecture? And at the same time, the
2:44hardware developer needs to know that
2:47under which software commands my
2:49hardware should should run them.
2:52So,
2:53instruction set architecture plays a key
2:55role in here. So, as I told you, it's a
2:58common language between the hardware and
3:00software.
3:02So,
3:04in here, there are two terms where the
3:06which are important. One of them is
3:08architecture.
3:09Architecture is the programmer's view of
3:11a computer.
3:13Uh like instruction, operand locations,
3:16like and or for example, operands. And
3:19microarchitecture is related to how to
3:22implement an architecture in hardware.
3:25So, as I told, instruction set
3:26architecture is the common language
3:28between the hardware developers and
3:30software developers.
3:33Uh Otherwise, we don't know. For
3:34example, when you write a software for
3:36the Intel,
3:37you cannot run it in on a ARM processor.
3:41Uh For this reason, there should be a
3:42common language, which is named as
3:44instruction set architecture.
3:49Is it clear? Did you understand that
3:51what
3:52instruction set architecture is? Okay.
3:55Instruction set archi-
3:57Now in the modern world, there are two
4:02instruction set architecture classes.
4:04One of them is RISC and other one is the
4:06CISC.
4:07So, they are classified into categories
4:10mainly. There are different instruction
4:12set architectures, but they are not
4:13common. They are not used much.
4:15And in RISC and CISC classes, there are
4:18lots of different variants of it.
4:22In this class, we are going to focus on
4:23RISC-based instruction set architecture,
4:26which is RISC-V.
4:27When you compare it,
4:30for example, in RISC,
4:33it stands for reduced instruction set
4:35computing.
4:37Its instructions are basic, simple.
4:42And it generates if you compile a code
4:45written code written, for example, in C,
4:48C++, or C#, when you compile it, it
4:50generates higher code size. This is a
4:53negative effect. But it's it's this
4:57processors, if you implement a processor
5:00that runs the RISC programs, it is
5:02its area and power consumption is less.
5:05Area is less, also power consumption is
5:07less. So, it is area and power
5:09efficient. And these RISC-based
5:11architectures are good for mobile and
5:13also for high-performance computing like
5:16desktop and laptop, it is also
5:18extending.
5:20So, it can perform better also.
5:22CISC is It is used mainly by Intel and
5:27AMD.
5:28It stands for complex instruction set
5:30computing.
5:32It has It consists of the advanced and
5:34complex instructions. When you compile a
5:36program
5:37by using CISC compilers, it generates
5:40lower code size, but its processors are
5:43very complex and power-hungry.
5:46These instruction set architecture good
5:48for high performance computing, but
5:50definitely not for mobile. And the good
5:53thing is that
5:55uh which is for for risk that we will
5:58see in this lecture in this class. Uh
6:00risk is also extending to the high
6:02performance computing. For example, when
6:04you look at the Apple uh the laptops,
6:07Apple was selling the laptops with x86
6:10uh
6:11and
6:12uh nowadays for the last 4 years, they
6:15start to ship also laptops with the risk
6:17processors, arm processors.
6:20When you look at the instruction set
6:22architectures, you I mentioned about the
6:25CISC. CISC is the actually the
6:29CISC belongs to AMD and Intel. It is
6:32x86. Okay, at it also has 64 variants.
6:36And when you look at the RISC side RISC
6:37side, there is RISC-V and arm.
6:41Uh arm is commercial. Uh there are two
6:44mainly two RISC instruction set
6:46architectures. One of them is RISC-V and
6:49arm. And arm is commercial. So, for
6:51example, you you can read the arm
6:53documents, but you cannot use this
6:57instruction set architecture arm
6:59instruction set architecture both the
7:00commercial one.
7:02Uh
7:02so,
7:03otherwise if you want to use it, you
7:05need to pay money to arm.
7:08It is proprietary. Uh so,
7:10and in here other one is alternative is
7:13RISC-V. RISC-V is open set instruction
7:15set architecture. It is like Linux.
7:18It is the hardware version of Linux.
7:20Linux is a open source operating system.
7:24Uh
7:25and RISC-V
7:26in software, of course Linux is
7:28software. RISC-V is like open source
7:30hardware.
7:32You can think about think so.
7:35So, in in this class, that's why the
7:37reason is that RISC-V is free and open
7:39source. We are going to focus on the
7:41risk five instruction set architecture,
7:43but mainly you can apply for example in
7:46this class we will see the complex
7:48processor architectures and you can
7:49apply it to other processor
7:52instruction set architecture also. You
7:54can use this methodologies to build a
7:56processor by using army instruction set
7:58architecture also.
8:03RISC-V, why we are seeing RISC-V?
8:05RISC-V is
8:07nowadays going very well.
8:10Its usage are increasing.
8:13In in the countries like for example
8:15China
8:16and other some European countries
8:19which are which they don't have any
8:22processor national processor, they are
8:24exploiting the RISC-V to build their own
8:26national processor because it is open
8:28source. There is a very huge open source
8:30community supporting this process
8:33instruction set architecture.
8:35For for this reason, it is global market
8:37is increasing
8:39very rapidly.
8:41And you can use it in many different
8:43domains.
8:45So,
8:47in overall nowadays, ASIC and in FPGA
8:50projects, 28 23% of those projects are
8:54using at least a single RISC-V core and
8:56it is increasing very rapidly.
8:59So,
9:01as for most of us as Turkish, if you
9:04want to build a national processor,
9:07then the RISC-V is the only choice. And
9:10we need to exploit the RISC-V.
9:12Otherwise, for example, we can okay read
9:15Intel's document and
9:17build a x86 processor,
9:20but we have to pay money to Intel or may
9:23not be sell.
9:25Most most likely they will not sell it
9:27sell it to us.
9:28And for the arm also, we need to pay to
9:31arm. But for if you are using RISC-V,
9:33there is a very huge open source
9:35community. They are supporting you.
9:38And its performance also increasing day
9:41by day. So, there is a good opportunity
9:45in RISC-V instruction set. So,
9:49it's very important. That's why we are
9:50opening this offering this class.
9:54And these lectures are just to
9:57introduce. These slides are just to
9:59introduce you instruction set
10:01architecture, what RISC-V is.
10:03Is it clear?
10:05You can ask in Turkish also. I can
10:07answer in in English.
10:11Okay.
10:14So, the course is about digital design.
10:18Yeah, I will mention about the course
10:19content.
10:20First, we will see digital design
10:23overview and system Verilog. And after
10:26that, we will start to look at RISC-V
10:28instruction set architecture. And after
10:31that, we are going to see the basic
10:34processor architectures in order ones,
10:36single cycle and pipeline in order ones.
10:39And after that, we will see caches and
10:41memory. We will
10:43look at the branch prediction. And after
10:45that, we will switch to out-of-order
10:47course. This is the important topic. I
10:49think this is the most
10:52beneficial content of this course.
10:56And after that, we will see some some
10:58information about the virtual memory and
11:00operating system, how to run
11:02operating system in an accord.
11:04And if we can find time, we will look at
11:07the SOC. We will look at the
11:09interconnect, peripherals, and GPU as
11:12empty and vector course.
11:14So, in overall, our aim is that, for
11:17example, in here, there is I put another
11:20Apple processor die shot. And in here,
11:23you can see the course. We I would like
11:26to show you how to build such a complex
11:28core.
11:30Of course, we will not be able to do it,
11:32but at least you will have a imagination
11:34that how can we build it. Maybe we can
11:37come together as a team, 30 40 people,
11:40we we will be able to build it. But at
11:43least you can
11:46imagine native.
11:48You can imagine
11:50how to build it.
11:52So, for example, you can see that in the
11:54internet, people are saying that okay,
11:56we are building this five course, but
11:58these are generally very very basic risk
12:00five course.
12:01For example, there is a competition
12:03Technofest chip design competition. And
12:06in this competition, people are
12:07designing risk five processor. They are
12:09very very small actually. They are not
12:11realistic. They are basic. Like for
12:13example, in this for example, projector
12:15controller, remote controller.
12:17Inside this remote controller, there is
12:20a small processor. It is just
12:23looking to the push buttons,
12:26sensing them, and sending the commands
12:27to the projector.
12:30You can use such processors in this
12:32remote controller, but not for high
12:34performance computing or in laptop.
12:37Inshallah, in our class, our aim is to
12:40look
12:41design complex processors.
12:45At least just to imagine how to build
12:46it.
12:51And in this class,
12:53you remember this picture of hierarchy.
12:56We will focus digital circuits, logic,
12:59micro architecture architecture and a
13:01little bit operating systems. In this
13:03class, of course, you have to know the
13:05knowledge of the digital circuits. At
13:06least you you took classes on second and
13:10third years. So, you need to know some
13:13information about digital circuits,
13:15but
13:17we we mainly in this class focus on the
13:20micro architecture and architecture.
13:23This is the course
13:26logistics information. In this course
13:31for 35% of the overall grade, we will do
13:35in-class quizzes.
13:36I will give seven quizzes in total and
13:39select highest five of them
13:41for grading.
13:43We will do one midterm exam, 25%, one
13:46final exam, 40%, and I will give you six
13:50homeworks, but it is optional. You don't
13:52You don't have to do it.
13:55So,
13:56the
13:58for advice for success in this course,
14:01just focus on learning,
14:03uh
14:04manage time, follow schedules, and don't
14:06postpone. In the case of a
14:09need, ask questions, even if it is
14:11basic. So, it is By the way, it is
14:14better for me to to this class
14:16interactive.
14:17I know it is a little bit hard in
14:19English, but we can try. Also, you are
14:22free to speak in Turkish, uh but if you
14:24can make the class interactive, I think
14:26it is much better. In here, I I put two
14:29proverbs. You can read it. It is
14:32unfortunately in in Turkish, uh but it
14:35says that
14:37free time is important. You need to
14:38evaluate it.
14:40And also,
14:42you need to also need evaluate or uh
14:46get the benefit from the uh free time
14:49before becoming busy.
14:53Uh what about the AI policy? You can use
14:57AI freely.
15:00No problem. Not in class, by the way.
15:01Not during the quizzes.
15:03Uh you can use
15:05large language models freely for
15:07learning, but it can easily mislead you
15:09if you expect more, because we are using
15:11it in our also in TUBITAK
15:14while we are building the complex ICs.
15:18Uh they are actually
15:20don't yield the best result. They are
15:22not giving the best results, maybe
15:24intentionally by the way, because for
15:25example, think about people for example,
15:28America is
15:29building a model large large language
15:31model.
15:32And you are asking this model how to
15:36gen- how to build a very super high
15:39performance respect
15:41processor.
15:42Uh do you think that
15:44does it give you the correct answer?
15:46Sometimes they are
15:48under performing performing
15:50intentionally. I know because one friend
15:53was working for these companies. For
15:55example, if you are asking for
15:58very
15:59for example, uh
16:01high-end questions,
16:04uh they are not answering uh
16:07fully. They are
16:09under performing.
16:12So, they are not explicitly answering
16:13everything.
16:16So, they are not yielding the best
16:18results may and most likely it is
16:20intentionally,
16:21uh but of course, you can use the LLMs
16:23for learning. So, you can ask for
16:25example,
16:26in the next phases of the courses, for
16:28example, you can ask LLMs how renaming
16:31works, for example, and you can check
16:33it. Uh
16:36Why we are not giving any homeworks?
16:39Because LLMs can do the basic RTL design
16:42tasks.
16:43Uh this is the fourth time we are
16:45offering this course, and in the in the
16:47first semester, in the first offering,
16:49it
16:50it was not able to do it.
16:53But day by day, uh they are progressing.
16:57Uh they are improving themselves, and in
16:58the last semester, we realized that most
17:01of the students are doing the homeworks
17:02by using the LLMs, and they are not
17:04learning. This was the problem. That's
17:07why homeworks are not graded. We will
17:09give it, but it is optional.
17:11Uh so, this is the new grading actually,
17:14starting from this semester.
17:19And the important point in here is that
17:21quizzes will be related to homeworks.
17:23So, working on the homeworks is still
17:25beneficial.
17:31At the beginning I mentioned that
17:33I am coming from TUBITAK
17:35and working for ITU as part-time.
17:40As TUBITAK,
17:41I am working for the integrated circuit
17:43design and training laboratory. We
17:45conduct research and teaching
17:47activities, but as
17:50employee in TUBITAK, as a researcher in
17:52TUBITAK, we conduct research and
17:53teaching activities at Istanbul
17:55Technical University because I am also
17:56at the same time part-time faculty in
17:58here.
17:59So, in here we are offering graduation
18:02projects. This is like
18:04a slide for advertisement.
18:06We are offering graduation projects.
18:09We have master and PhD students in here.
18:12Also, in TUBITAK we are offering
18:14internship and fellowship. By the way,
18:16in digital domain, for example,
18:19around 60% of the researchers graduated
18:22from this course in in my team, in my
18:25research team.
18:26So, this course is actually beneficial
18:29for your for your requirement
18:31in TUBITAK.
18:35And also we are offering two courses as
18:38TUBITAK. One of them is this course.
18:41This course is named as RISC-V
18:43architecture and processor design, but
18:45starting from the next semester we will
18:47make it EHB course,
18:50inshallah, hopefully. And it will be
18:52named as processor architecture and
18:54design. And in this course, it is a the
18:57content will be the same. So, we will
18:59see RTL implementation of a complex
19:02high-performance processor architecture.
19:04And after this course, we will offer
19:07this course during in the spring
19:09semesters, and in the fall semesters we
19:12are going to offer the associate design
19:14and physical implementation course. And
19:16in this course, we are going to
19:17physically implement the processor that
19:20processors that we designed in the
19:22previous course.
19:23So, in this course, we will focus on the
19:25associate design and physical
19:26implementation at TSMC 16 nanometer
19:29technology.
19:33So, this course will be
19:35about the design and the next course
19:37will be about the physical
19:39implementation and associate design.
19:41Because
19:42in this course, we are mainly we focus
19:44on the core of a processor. Uh but core
19:48itself is not much meaningful. You need
19:51to build a associate system because for
19:54example, you are
19:55In the next lectures, we will see in
19:57detail, but
19:58if you build a core processor core, of
20:01course, you need to for example, connect
20:03screen to this core,
20:05uh keyboard to this core. So, associate
20:07environment is the place that you are
20:10connecting these peripherals to this
20:12core. So, it is also very important. Uh
20:14actually, associate is providing you to
20:16methodology to interact with the outside
20:18world. Core itself is not enough.
20:21Core is the like brain, but you need
20:23hands also at the same time. Like
20:29Any question?
20:42Yes.
20:44So, before starting to the class, I will
20:47mention a little bit about integrated
20:50circuits and its importance also.
20:54Uh so, as you know, integrated circuit
20:56consists of transistors.
20:58Uh in here, we have a For example, this
21:00is a transistor. It's like
21:02uh a switch.
21:04Uh
21:06If you
21:08apply a voltage to the gate, it passes
21:11current. And if you don't apply, it's
21:14just
21:15not pass the current.
21:19So, with the advent of the technology in
21:21the technology, these
21:24transistors can be built in a very small
21:26dimensions, like 14 nanometer.
21:30So, compared for example, you can build
21:32a transistor and its size can be for
21:34example, like 7 nanometer, 10 nanometer.
21:36It can be very, very small.
21:38So, compared to human hair, which is
21:41around 90,000 nanometer thickness,
21:44uh you can fit maybe
21:47thousands of them inside a human hair.
21:50So, by combining these transistors,
21:54we are building the logic gates and
21:56unlock devices. For example, in here,
21:59there is a basic AND gate.
22:01And you can think that it consists of
22:03six transistors. When you compute its
22:05area, it's very small.
22:08Like for example, 100 nanometer, you we
22:11can say. So, it is
22:13in a 100 nanometer square meter for
22:16example, you can build very simple logic
22:18gate that can perform the AND gate. And
22:21by using these AND gates and combining
22:24them, we are building more complex
22:26circuits like adders, multipliers.
22:30And at the same time, analog devices are
22:32also built by using just transistor.
22:35Of course, analog can also use inductor
22:38and other components.
22:40And then by using these very tiny
22:43transistors and combining billions of
22:46them, we are building the integrated
22:48circuits.
22:51And in terms of the signal, there are
22:54two domains, as you know. One of them is
22:57analog domain and one of them is digital
22:58domain. Digital domain is like
23:00abstraction of the domain. Analog is
23:02continuous,
23:03like 0, 0.1, 0.2, 0.375
23:07V,
23:08but digital is between two values. It's
23:11abstract version of the analog. This is
23:13one or zero. And all processors works as
23:17digital.
23:18So, in this class we are going to focus
23:20on the digital domain.
23:23How we are building digital or
23:25mixed-signal integrated circuits?
23:28In here, I will mention briefly.
23:30Normally, it is impossible. For example,
23:33one one CPU consists of maybe a billion
23:36of transistors, and it is impossible to
23:38connect them by hand.
23:40So, generally we write
23:43hardware
23:45We write actually code to to describe
23:47the processor.
23:49And this is named as hardware
23:51description languages.
23:54And after writing this hardware
23:56description languages, we are synthesize
23:58it. It's like compilation. We compile
24:01it.
24:02And after that, after the compilation,
24:05we convert it in a format that can be
24:09fabricated physically.
24:11So, we are converting it into in a
24:13physical format.
24:15At the same time, if you want, you can
24:17put
24:18analog circuits inside.
24:21And build a mixed-signal integrated
24:24circuit, digital or mixed-signal
24:25integrated circuit. But, the important
24:27point in here is that
24:29you are not building the processor by
24:32combining billion of transistors. You
24:34are just writing code. We are describing
24:37the processor by writing code.
24:44And after this compilation, you can
24:46think it as a compilation.
24:48After com After these steps, you can
24:51send it to the fabrication and produce
24:53the chip. This is the digital or
24:55mixed-signal integrated circuit design
24:57flow in general.
24:59Uh what about analog integrated circuit
25:01design? In analog integrated circuit, we
25:03are still using transistors, but this
25:06time we are designing it by hand. We are
25:09putting the transistors and shaping
25:11them. For example, specifying its
25:13dimensions. We are connecting them.
25:16And
25:17after that, we are writing We are making
25:20it ready for the
25:21production and sending it to the
25:23fabrication for fabrication and getting
25:26the chip.
25:30The difference is that mainly in digital
25:32integrated circuit design, we are
25:34writing the
25:35hardware description language code uh to
25:38describe our processor complex IC, and
25:41then like compiling it. We are just
25:44synthesizing it. It's like compilation.
25:46And in analog integrated circuit, people
25:48are doing
25:50uh handcrafted job. So, they are just
25:53sizing by hand.
25:55They are combining, putting the
25:56transistors, and combining them
25:59uh by hand.
26:01And also, uh there's another
26:03methodology, FPGA-based digital system
26:05design. This is different than the
26:07integrated circuit design, because
26:08integrated circuit is the chip itself,
26:11but FPGA is a little bit different. In
26:13FPGA, there is a chip inside here, and
26:16inside this chip, you are
26:18uh putting your HDL, hardware
26:21description language
26:23uh code.
26:25Uh I will not go into the details, but
26:27in here, in this methodology, it is not
26:29like this
26:30digital integrated circuit design,
26:32because in here, you are designing the
26:34integrated circuit itself.
26:36But in FPGA-based digital system design,
26:38there is a chip, and you are putting
26:40your HDL functionality into this chip,
26:42and somehow this chip functions as you
26:45described.
26:47You are still writing hardware
26:48description language in here.
26:51But its flow is different.
26:56So,
26:57computation and integrate circuit, I
26:59will mention about the overview and
27:01importance. Since, for example, you can
27:04think about
27:06you are running,
27:08for example, different software
27:10applications,
27:11like health, for example, health care
27:13systems, Chrome, or WhatsApp, for
27:15example, and these applications are
27:18running running over an operating
27:19system.
27:21And this operating system runs on a
27:23integrated circuit.
27:25There is a chip, and you are running
27:26this operating system in this chip.
27:29And this chip is produced somewhere
27:31else, for example, in outside, in
27:33Taiwan, or in United States.
27:36So, the important thing in here is that
27:39if you want to build
27:41if you want to use dependable, secure
27:44software, you need to be sure that
27:47all of the
27:49levels under the software
27:53must be developed by you, or must be
27:56developed by a secure people.
27:59So,
28:01that's the reason the the
28:04important point in here is that, for
28:06example, if you want to build a secure
28:08phone,
28:09or secure
28:11software,
28:13unless the hardware is not secure, you
28:15cannot provide 100% security. For this
28:18reason, it is very important to build
28:21their own IC. As as nation, it's for a
28:25nation, it is very important to build
28:26their own IC.
28:30Otherwise, for example, we can say that,
28:32"Okay, we have Pardus operating system,
28:34but it is not 100% secure." And I will
28:37mention about some examples
28:39about the security and importance of
28:42this building their own chips. By the
28:44way, Turkey is not building their own
28:45processor.
28:47That's why we are giving this class to
28:49to create an ecosystem and to do
28:52movements in this direction to build our
28:55own IC, own processor, like our own
28:58Intel processor. We can do it.
29:00Uh,
29:01unless hardware is made designed by us,
29:05uh, the software is not secure. This is
29:07the key point in here. What can be done?
29:09For example, you can purchase a chip
29:11from somewhere else and it can be
29:13counterfeit chips.
29:15It's a fake chip, like
29:16uh, people can put backdoors.
29:19It is very common, by the way. Uh, you
29:21can they can put backdoors inside this
29:23chip
29:24and they can get the control of this
29:26chip anytime. Uh, it's up to them.
29:29Uh, then they can intentionally life
29:32reduce the lifetime of this chip. For
29:34example, you are putting a chip inside a
29:36plane
29:38and you are thinking that this chip last
29:4010 years, but they intentionally reduced
29:43its lifetime to 4 years. So, after 4
29:45years, maybe the chip will malfunction.
29:49So, it's a catastrophic case.
29:51Uh, and I mentioned about also
29:53malfunction. They can change the
29:54functionality of the chip.
29:56So, that's very important. Why it is
29:58very important design and also produce
30:01our own chips as nation.
30:04Otherwise, only building to software is
30:06not enough. For example, we can build
30:08our own operating system, but it's not
30:10enough.
30:11Uh, we need to run them in our own
30:14integrated circuits and even we need to
30:17build these integrated circuits in here.
30:22Uh, let's see some examples what is
30:23happening if you cannot
30:25if you don't produce design your own
30:28chips. There is a
30:30some cases.
30:32Uh, one of them is in 2007. Uh, Syrian
30:36S-300s were disabled due to the
30:38backdoors within the networking chips.
30:40Actually, Israel disabled their
30:42uh,
30:44network chips, actually, uh
30:46by using their backdoors. So, they chip
30:49couldn't communicate. They couldn't
30:50sense Maybe they sensed the planes, but
30:53they couldn't inform the center.
30:56Because they hacked the They hacked the
30:59communication chips.
31:01Uh as far as I remember, it was It was
31:03Mellanox IC
31:05network chips. And they they used the
31:07backdoors of inside this chip.
31:10And you know, pager attack in Lebanon in
31:122020, for they they hacked the chips.
31:16And at any time, they they convert this
31:19phone to a bomb.
31:22You can Google it. If you don't know the
31:23in detail, you can Google it in in
31:26Google it and see the details.
31:28And also, restriction is also an
31:31another important thing in here. For
31:33example, you cannot buy If you want to,
31:36for example, buy a very high-speed
31:38analog-digital converter, you cannot buy
31:40it because they need to allow to sell it
31:43to you.
31:44And most likely, they are not allowing.
31:45For example,
31:46I know in processor, for example, if you
31:50if you want to purchase a processor, for
31:51example, 4 GHz, 5 5 GHz, very
31:54high-performance processor,
31:56uh you need to
31:58fill lots of documents, and you are
32:00getting permission. Otherwise, they are
32:02not selling you. And you know, in for
32:04example, GPUs, they were not selling to
32:07GPUs to
32:08China. They were selling
32:10not high-end GPUs to China, maybe around
32:132 3 years ago. So,
32:16they can easily restrict it. For this
32:18reason, we need to design our
32:19high-performance chips.
32:21And there are in here, you can read some
32:23news. I put some news. It is very
32:25important. For example, in Turkish
32:27drones, uh they found some parts, and
32:30they apply
32:32They stopped selling the some parts uh,
32:35to Turkey.
32:37So, and of course, as I told you, they
32:40they are registering the highest
32:41technology products.
32:44And also, I put uh, two news here. One
32:47of them says that uh, it was about the
32:49chip war around 2 years ago. Uh, it says
32:53that who controls the chip controls the
32:55world, uh, the silicon cold war. The the
32:57war actually between the China and
32:59United States mainly based on the chip.
33:02Uh, they are saying it as a silicon war.
33:06And most likely you will see this video.
33:08I I don't know. Yeah, you can read the
33:13uh, subtitle in here.
33:15For example,
33:16he is saying that if you are a holding a
33:18cell phone, it's a piece of Israel. He's
33:20saying that.
33:22Uh, because most of the chips inside
33:24this cell phone are built by them
33:26somehow.
33:34So, you can check them offline.
33:41So,
33:43that's all.
33:45Uh, in this class I told them that in
33:47this class we are going to see how to
33:49design very complex
33:51uh, chips.
33:53Uh,
33:54so how can we do it? How How How do we
33:56design things that are too big to fit in
33:58one person's head at once? Uh, there are
34:00three design methodologies in here.
34:03Uh, abstraction discipline uh, and there
34:05are three ways as I
34:07told. Uh, the important thing here in
34:10here is that hierarchy. So, we need to
34:12divide the for example, think even this
34:15core is very complex.
34:17Uh, we need to divide it into modules
34:19and sub modules and this each sub module
34:21for example, designed by a group of
34:24people.
34:26And modularity in here is important. Uh,
34:29having well-defined functions and
34:31interfaces between them.
34:33For example, this core is communicating
34:35with this core, and there should be a
34:37well-defined interfaces for them.
34:41And regularity. You look at If you
34:43design this core zero, and there are
34:45lots of cores in here, they are the
34:47same. You are just duplicating them.
34:51Replicating them, and it's the already
34:53half of the chip, for example. Half of
34:54the chip is the same of this core zero.
34:57And most likely these cores are very
34:58similar to this core. Only some
35:00configurations are different, and you
35:03are building most of the chips already.
35:05So, regularity is also important.
35:09So, we are following three ways in here:
35:11hierarchy, dividing everything into
35:13modules and submodules, modularity, uh
35:16there should be a well-defined functions
35:18between these modules, and regularity.
35:22So, it's like
35:23abstraction and discipline. Abstraction
35:25means that like it's related to
35:28hierarchy, also.
35:31So,
35:33in here we started Okay.
35:36We can continue a little bit more, and
35:38we can give a break.
35:41We didn't start the class yet. I will do
35:44some review on digital systems,
35:47uh and we will start with binary
35:48numbers.
35:49Uh most likely you are familiar with
35:51these concepts, and
35:54but let's do a some review on on it.
36:00Let me check this one.
36:03Okay.
36:25So, the first topic the in the in the
36:27radio is about the binary values.
36:30Uh there are two discrete values
36:33uh
36:33for in digital domain, one and zero.
36:36Everything consists of one and zero.
36:38Uh one is like voltage is on and zero is
36:42like voltage is off.
36:44Uh they are named as true or false or
36:47high and low or zero and one. There are
36:49different names for it for them.
37:00Let me check, please.
37:08So, this is a circuit used the voltage
37:10levels. Uh zero is generally low
37:12voltage. Uh zero is low voltage and
37:14correspond to ground and one is high
37:17voltage correspond with the VDD.
37:19And these levels corresponds to a bit,
37:22binary digit.
37:24And by using these bits, actually
37:26computers are as I told you consist of
37:28one and zeros. Uh they are not competing
37:31in decimal domain. Decimal is base 10.
37:34The numbers between zero and nine uh
37:36corresponds to base 10, but computers
37:39only know zero and one, binary system.
37:42And
37:44corresponding to the human uh humans use
37:47the decimal numbers. Uh actually these
37:49decimal numbers are represented in
37:51computer in one and zeros.
37:53And in here you there is a
37:55correspondence. Actually, you'll see
37:57there is a
37:58uh decimal number
38:00uh
38:01correspond this number and decimal
38:04equivalent of it. And binary number is
38:07like this one. It is also in decimal
38:09everything is 10 to the X, for example,
38:12the
38:13uh value of a digit in here is a 10 to
38:16X. The X is the digit's position.
38:20In a similar manner, in binary number,
38:22it is
38:23two to the X, where X is the
38:27digit number.
38:29So, for example, 1101,
38:32which is correspond which corresponds to
38:341 * 2 to the 3, because this this one is
38:37three, third one, plus 1 * 2 to 2, plus
38:410 * 2 to 1, and 1 plus 1 * 2 to 0, and
38:45it corresponds to 13.
38:47Actually, this binary number, for
38:48example, you put it in a computer, this
38:51corresponds to 13 in decimal system.
38:54And, as I told you, computer only
38:57understands the binary numbers. People
38:58are trying to build ternary or
39:00quaternary computers, but now the only
39:03there are commercially binary numbers
39:06are used by the computers.
39:10If don't know, you can interrupt me, but
39:13this course I will do a very quick
39:15review. And this no this course actually
39:19assumes a good knowledge on this digital
39:21systems.
39:24And in here, I put some examples to
39:26binary to decimal conversion and decimal
39:28to binary conversion. How can you do it?
39:31You can check the slides, and if you
39:33have a question, also you can ask.
39:35But,
39:37if you have a n-bit binary number, it
39:39can represent two to the n numbers,
39:41different values, and it represent
39:43between zero to two to the n minus one,
39:46the range between them.
39:48For example, three-digit binary number,
39:51it can
39:53it is between 000 and 111. So, there are
39:56eight possible values between these two
39:59numbers.
40:03Hexadecimal numbers is also very
40:05important. We are using while writing
40:07while building the processor, we are
40:09using hexadecimal a lot.
40:11Hexadecimal corresponds to base 16.
40:13Until now, we saw base 10, base two,
40:16base 16 is the another
40:18and it's named as hexadecimal numbers.
40:21It's a short hand for binary. How it is
40:23a short hand? Because four digit binary
40:26number corresponds a digit in
40:27hexadecimal number.
40:29For example, this is a hexadecimal
40:31number. By the way, hexadecimal number
40:32is between zero and 15.
40:34Uh decimal is between zero and nine,
40:37binary is between zero and one,
40:39uh and hexadecimal is between zero and
40:4215. And after 10, people are represented
40:45as a A B C D E F.
40:48And each four bits in binary corresponds
40:51to a digit in hexadecimal.
40:54So, in order to convert a hexadecimal to
40:56decimal, it is the same. Uh
40:59in here, our base is 16. So, 16 * 16 uh
41:04power of
41:06uh the digit position times the value.
41:08For example, it is 4 * 16 squared plus
41:13uh 10 * A corresponds to 10. 10 * 16
41:16plus uh 15.
41:18F E F corresponds to 15 and this is the
41:20decimal conversion.
41:22So, for example, as I told you, a
41:25hexadecimal number corresponds to four
41:27four-bit binary number. And for four,
41:30for example, it corresponds to 0 1 0 0
41:33because this is four actually in
41:35hexadecimal.
41:37For example, A is 10 and when you look
41:39at this four digit, it is a it
41:41corresponds to 10. 2 + 8, it is 10.
41:46Let me activate this one.
42:04And in digital systems, we have some
42:07terms. Bits, we we know zero and one.
42:11Uh bytes and nibbles. Uh, byte
42:14corresponds to eight bits. Most likely
42:15you know about the RAM. Uh, for example,
42:18your RAM is can be described in terms of
42:21bytes. Uh, so bytes correspond to eight
42:24bits. Nibble is the half byte. It is
42:27four bits. And half is 16 bits. A word
42:30is 32 bits. Double is 64 bits.
42:35Uh, people also using kilo, mega, giga,
42:37tera, peta, exa.
42:39Uh, these are 2 to the 10, 2 to the 20.
42:42And this is the approximate value in
42:45decimal.
42:47For example, if you say that 1 kilobyte,
42:49uh, it is actually 2 to the 10 to 2 to
42:5210 byte.
42:55In a number,
42:57uh, the leftmost one is the most
42:59significant bit and rightmost is the
43:02least significant bit.
43:03Uh, this says eight-bit number, it is a
43:05byte. And half of it is a nibble. Uh, we
43:08are not using nibble much.
43:10Uh, and this is a hexadecimal number,
43:12for example. This is the least
43:14significant byte in this hexadecimal
43:16number. This is eight-bit and this is a
43:18byte. And this CE is the most
43:21significant byte. In here, for example,
43:23there is 64-bit number.
43:26This is a 64-bit number. And when you
43:29separate it as bytes, each two of them
43:32is a byte.
43:33Uh, sorry, this is a 32-bit byte. 30-bit
43:36number because there are four bytes in
43:38here.
43:42While doing arithmetic operations in
43:44digital systems, we use the two's
43:46complement.
43:47Uh, so in two's complement number, we
43:50have a number like this one, XYZ, for
43:53example. And the most significant bit,
43:56the leftmost one, is the uh, sign bit,
44:00like sign bit.
44:01So it has a weight of minus 2 to the M
44:04minus 1. So if this is one, for example,
44:07uh,
44:09its weight is -2 and -1. It is if it is
44:13zero, its weight is when you go
44:16multiply it with zero, it is zero.
44:19So, whenever is a number is minus, this
44:22bit is one.
44:23So, in this representation in two's
44:25complement representation, if you have a
44:28number, you can use this formula to find
44:30its decimal correspondence as signed.
44:33And in this representation, most
44:35positive four-bit number is 01111, okay?
44:38Because
44:39this is zero.
44:41When you look at here, it brings zero,
44:43and this one is
44:454 2 1. When you sum them, it is seven.
44:49And most negative four-bit number is one
44:52and three zero. So, because why it is
44:54so, when you look at here, -2 and -1,
44:59-2 power -1.
45:01So, it is -2
45:04power three, it is -8.
45:10By the way, this formula is like this
45:12one, okay?
45:13So,
45:15what about this 1111?
45:18It is like -8 plus
45:214 + 2 + 1, so it is -1. It is not the
45:25most negative one.
45:27The most negative one is this this one
45:29for this reason in two's complement.
45:33So, the range of an n-bit two's
45:35complement number is between this.
45:37And in order to reverse the sign of a
45:39two's complement number, you need to
45:41invert the bits and add one. So, you
45:44need to make this zero to one, this zero
45:47to one, this zero to one, and this one
45:49to zero, and after that, add one in
45:51order to reverse its sign.
45:55So, invert the bits and add one. This is
45:57the method one. In method two,
46:00for example, this is a number, 0101
46:040.
46:05You want to invert the sign of this
46:07number. You start look start to look at
46:09from this direction. Whenever you saw
46:11first one, just
46:13invert the bits after [snorts] after
46:15this bit.
46:17Okay?
46:20So, in here I put four-bit
46:22representation of a two's complement
46:25numbers.
46:31So, in here we can give a break.
46:35Uh I was planning to give break at 30.
46:38So, we can give a break. Maybe we can
46:40start at
46:421:50.
46:44Okay?
46:46After 18 minutes.
47:01And then
47:02That's the way
47:03uh we we will Okay. Reviewing the
47:06digital systems.
47:07And
47:09we will see the number systems. So, you
47:11need to know them. I am not trying to
47:13teach you. I am just trying to remind
47:15you.
47:16So, but you need to know these
47:18uh concepts.
47:20Digital systems, binary numbers,
47:21conversion, binary number conversion,
47:23hexadecimal numbers, and these concepts,
47:25and two's complement. This is very
47:27important.
47:28Uh you need to know them.
47:30And also, you need to know the
47:32fundamentals of transistors.
47:34So, transistors
47:36uh in here there are two types of
47:37transistors, N-MOS and P-MOS.
47:40Uh and N-MOS and P-MOS is the different
47:43working behaviors. In N-MOS, if the you
47:46apply a zero
47:48to gate,
47:49uh it's not conducting.
47:52Uh so, if here here is zero, it's not
47:55conducting.
47:57So, it means that no connection between
47:59the source and drain. Source and drain
48:00is the like for example, it is input and
48:04it goes through the it comes from drain
48:06and goes through the source. And if we
48:09apply zero to gate, it's not conducting.
48:11If we apply one to gate, it's
48:13conducting. There is a channel in here
48:15and it connects drain to source. So, the
48:18information can flow from here to here.
48:21And PMOS is the opposite. If it is uh
48:25gate is zero, it is on. So, if you apply
48:27zero volt to here, it is on. It's
48:30conducting. If you apply one to here, it
48:33is not conducting.
48:35And by using this NMOS and PMOS
48:38transistors, at the beginning I
48:39mentioned about the transistors, but
48:42transistors is two types, NMOS and PMOS.
48:44And by using both these two transistor
48:47types, we are building the logic gates.
48:50How we are building? Uh there are two
48:53networks. One of them is pull-up network
48:55consists of PMOS transistors and other
48:57one is a pull-down network consisted of
48:59NMOS transistors. Pull-up network
49:01devices are connected to the VDD power
49:05source and NMOS
49:07uh
49:08ones are connected to pull-down network.
49:11And we are applying to input to here and
49:14then getting the output from here.
49:17So, the important thing in here is that
49:20for NMOS, uh it pass the zero. It means
49:24that V VSS or ground
49:27uh in a good way.
49:29This NMOS transistor passes the VSS well
49:32and this PMOS transistor passes the VDD
49:34well.
49:37For example, in here we have a not gate.
49:41And in this not gate
49:43uh for example
49:45uh this not gate consists of these
49:48transistors, one PMOS transistor in
49:50here, one NMOS transistor in here. And
49:53NOT gate is actually basically does if
49:55you apply a zero,
49:57it converts it to one and if you apply
49:59one, it converts it to zero. So,
50:01whenever you apply a zero to this A, Y
50:04gives one. It inverts it.
50:06So, when you look at this
50:09uh the logic gate correspondence of it,
50:12transistor correspondence of it, there
50:14is a PMOS gate in here and NMOS gate in
50:16here. NMOS is connected to GND, ground,
50:18and PMOS is connected to VDD.
50:20Whenever you apply a zero to A, it means
50:23that
50:24Y is the output in here. Whenever you
50:26apply A to here,
50:28it means that NMOS gate is disconnected,
50:31transistor is disconnected, so there is
50:33no connection
50:35to this Y point to the ground.
50:37But, this PMOS transistor contacts.
50:40So, it passes this VDD voltage to Y. So,
50:44it gives one.
50:46What about one? If you apply one to
50:48here, in this case, this PMOS closed,
50:51NMOS passing. So, this ground is
50:53connected to Y, it gives zero.
50:56This is the This is the case for the
50:58base inverter, but it's same for the
51:00AND, OR, XOR, any other gates.
51:04For example, this is a correspondence
51:06for NOT NAND gate. It is NOT AND gate.
51:09So, you can also build this by using the
51:12same pull-up and pull-down network
51:14structure, you can build also NAND gate.
51:18But, this time it has
51:20two inputs and one output.
51:22We are using four transistors. These
51:24PMOS transistors are connected as serial
51:26and NMOS transistors connected as
51:28parallel
51:29in here and it corresponds to NAND gate.
51:33So, when you look at the DC
51:34characteristics of, for example, take an
51:37example an ideal buffer. A buffer is
51:39like actually two inverters connected to
51:42each other. So, whenever you apply zero
51:44to here, you you get one you are getting
51:46one from here and then again getting
51:48zero to here. So, when you look at it,
51:50it is a big buffer.
51:52Whenever you apply zero to here, you are
51:53getting zero.
51:55The good thing in here is that
51:58it is actually For example, this zero is
52:00a little bit weak.
52:02For example, people are using buffer to
52:04to
52:05strengthen
52:06signal.
52:08For example, you are applying zero to
52:09here, but it is like maybe 0.1 V.
52:12Because think
52:15in here, for example, there are two
52:17voltage
52:18Off means zero, on means VDD. For
52:21example, you can say that 0.8 V. The V
52:25on is 0.8 V. It is 1 V. Corresponds to
52:28logic one, and this one corresponds to
52:30logic zero.
52:32Buffer is used it for for example,
52:35sometimes due to the noise,
52:38it is not exactly zero, but it is a
52:40little bit higher than zero, 0.1, for
52:42example. So, whenever you apply 0.1
52:44point here,
52:45and this is a active
52:48component. It has a VDD and VSS
52:51connection, and VSS is zero.
52:55It eliminates the noise in here and
52:56gives zero to here. Or maybe in other
52:59way, for one, for example, you are
53:01applying maybe 0.7 V. A little bit
53:03noisy, not exactly 0.8 V.
53:06But in here, when you pass it through
53:09the buffer, you are getting exactly like
53:110.8 V. It's You are making the signal
53:14stronger.
53:15That's why people are using buffer. And
53:17when you look at the characteristic of
53:19this buffer, normally ideally it is like
53:22exact zero, and it passes one.
53:26So, if it is zero, it gives zero. If it
53:28is one, it gives exact one. But it is
53:30not always so.
53:32In the real case, it is like so.
53:35In real case, also, we are As I told
53:37you, we are not getting exact zero. We
53:39are getting something between zero and a
53:41low threshold voltage and also for the
53:45output we are getting something very
53:46close to high
53:49logic one volt but not exactly.
53:51So it is real characteristic actually in
53:54in in such a way.
53:58Normally I told that 0.8 volt Normally
54:02as I told you zero and one is the
54:04logical correspondence but actual
54:06voltage correspondence are different.
54:08For example, for zero it is generally
54:10always zero but for one it's changing.
54:13In the previous chips, for example, in
54:1619 and 70s it was 5 volt. Now in for
54:20example in our to into bit act we are
54:23designing
54:25circuits with
54:270.8 volt. At 0.8 volt it corresponds to
54:29logic one.
54:31So it is decreasing by the
54:35improvement in the technology this
54:37voltage is decreasing. This The reason
54:40why people are trying to decrease it due
54:42to the power consumption. They are
54:43trying to decrease the power consumption
54:45of integrated circuits.
54:46Now
54:48in maybe very in very high-end
54:51technology notes like 2 nanometer 3
54:54nanometer technology notes people are
54:55using around 0.7 and 0.6 volts. It's
54:59very low at these notes.
55:03So VDD is dropping
55:05by time.
55:10And
55:11it depends on the logic family. For
55:13example, for TTL logic family the it is
55:16between zero and five. For CMOS it is
55:20yeah a little bit different.
55:21Uh
55:23And LVTTL it is low voltage TTL the VDD
55:26is 3.3 and for LVC most it is 3.3 but
55:30there are small differences between the
55:33ranges.
55:34Uh Uh, because the issue in here is that
55:37since this is a real buffer circuitry,
55:41it is not ideal.
55:43In in a computer in digital domain, it
55:46is not exactly at zero or 0.8 8. It is a
55:51little bit closer to zero.
55:53So, for example, it is between zero and
55:55zero one.
55:57You can say it that this real buffer
55:59pass
56:00passes it as zero.
56:03But, for example, what about 0.3?
56:06If it is 0.3, it is not allowed.
56:10So, there shouldn't be any
56:13transistor working at this voltage,
56:15giving
56:16output at this voltage. So,
56:19the computer chips generally says that
56:22this range is corresponds to zero and
56:25this range corresponds to one.
56:27And between them, it is forbidden. You
56:30are not driving any transistor between
56:31these range. You need to actually design
56:34your circuitry accordingly. But, as
56:36digital designer, we are not dealing
56:37with it because I mentioned that we are
56:39doing abstraction. We are not designing
56:40analog circuits. Normally, everything is
56:42analog.
56:43For example, we are building we are
56:44using the transistors and building the
56:46logic gates. Actually, logic gates are
56:48itself inherently analog.
56:50But, we are abstracting them and using
56:52as digital. So, we are not dealing with
56:54analog.
56:55Uh, but this is the fundamental. You
56:57need to know the fundamentals.
57:00But, of course, we will not deal with
57:01any voltages. For everything everything
57:04for us is zero or 0.8 VDD and ground.
57:10And there are some
57:12concepts for logic gates also. We
57:14mention about one and zero in here. Uh,
57:17voltage on and voltage off.
57:19And there are two values also in logic
57:22gates. One of them is unknown and one of
57:25them is floating.
57:28Uh, for floating, it is very easy. It is
57:30a easy. It is high It means high
57:33impedance, open. So, for example, if you
57:35have a wire
57:37if for example, you have a wire and you
57:39didn't connect anything to this wire, so
57:41you don't know whether it is zero or 0.8
57:44or anything between them. You don't know
57:46anything about this voltage.
57:48So, it is floating, actually. It is high
57:50impedance. It is open.
57:55So, what about contention?
57:57Uh
57:58contention
58:00uh is the case where the circuit tries
58:02to drive output to one and zero at the
58:04same time.
58:06It is still not known.
58:08For example, in here I have an inverter
58:11and I have another inverter in here. For
58:15uh in here, I'm driving one, so it tries
58:17to drive zero to this Y. And for in from
58:21here, it tries to drive one
58:24to here.
58:25And still
58:26it we don't know
58:28the output on here. But, this one is a
58:30different case. It is named as
58:32contention. Circuit tries to drive
58:34output to one and zero at the same time.
58:37Floating is a little bit different. In
58:39floating, we are not driving. It is
58:41open.
58:42And both of them are unknown. We don't
58:44know.
58:46Uh for contention, actual value is
58:48somewhere somewhere in between. Uh it
58:50could be zero or one, but forbidden.
58:53Uh
58:54its actual value can change depending on
58:56the voltage, temperature, time, and
58:58noise.
58:59Uh so, this is very problematic because
59:02it it causes excessive power
59:03dissipation.
59:05Because you are providing current to
59:07here and this one is consuming this
59:08current. So, this is
59:10causes excessive power dissipation.
59:13And this X is also used for
59:15uninitialized values and don't cares.
59:18And floating is also same as I told you,
59:20but in here we are not driving anything,
59:22so it is safer. This floating case is
59:25safer.
59:26Uh
59:27in here, the message that I'm trying to
59:29give you is that not everything is one
59:31or zero. You can You need to know the
59:33knowledge of X and Z also. Z is means
59:36that not driving and X means that
59:38unknown. We don't know the value in
59:40here.
59:43For example, most likely you know
59:45three-state buffer. Three-state buffer
59:47has an input enable. And whenever this
59:50enable is one, this A passes to Y.
59:54But whenever this E is zero, this Y is
59:56floats. It is not connected. This A is
59:59not connected to Y. So, Y floats.
1:00:03Nothing drives Y. So, in this case, if A
1:00:06is zero, we are showing the Y as Z. And
1:00:09whenever E is one, A is passes through
1:00:12Y.
1:00:14This is three-state buffer. It's very
1:00:15useful actually. Three-state buffer is
1:00:17very useful if you are building a bus,
1:00:18for example.
1:00:20Uh, for example, you have a signal in
1:00:22here and this signal is right by
1:00:25different sources.
1:00:27But not at the same time.
1:00:29So, for example, A is driving this bus,
1:00:32B is driving this bus, C is driving this
1:00:34bus, but not at the same time. So,
1:00:36three-state is useful. So, if you put a
1:00:39three-state buffer in here
1:00:41and only at any time one of them has E
1:00:44is one and other one is E is zero. And
1:00:47in this way, for example, if
1:00:50A's three-state buffer is one, this A
1:00:52drives this bus. So, it is very useful
1:00:54circuit.
1:00:57So, in here we have a diagram that shows
1:00:59it. For example, in here we have a
1:01:01shared bus and this bus is driving by
1:01:03processor, video, ethernet and memory.
1:01:06And at any time one of them
1:01:09sets the enables to one and other one
1:01:12sets it as zero. And this one drives
1:01:14this bus.
1:01:17But as a practical information,
1:01:20generally
1:01:21or almost always we are not using
1:01:23tri-state buffers in our
1:01:24high-performance integrated circuit
1:01:26processor designs. We are not using it
1:01:28because tri-state buffers lack in
1:01:30timing.
1:01:31So, its timing is not good. For example,
1:01:33if you want high frequency like 1 GHz, 2
1:01:35GHz, 3 GHz, tri-state buffer doesn't
1:01:38provide enough frequency to you. So, we
1:01:39are not using tri-state buffers.
1:01:42But, it is useful if you are using a
1:01:44maybe low frequency uh processor trying
1:01:47to build a low frequency processor,
1:01:49tri-state buffer can be useful.
1:01:52Logic gates, there are two types of
1:01:54logic gates. One of them is for
1:01:55combinational logic gates, other one is
1:01:57sequential. Combinational logic gates
1:01:59are memoryless. There is no memory. It
1:02:01has no state actually. We are not
1:02:03keeping any state. We are just applying
1:02:05input and getting output. There is a
1:02:07functionality inside in here.
1:02:10Like AND gate, for example. AND gate, it
1:02:12has a no state. It has two inputs, one
1:02:15output. Whenever we change the input,
1:02:17it's changing the output, but there is
1:02:19no state inside here. For example, it's
1:02:20not keeping the previous value of the
1:02:22output.
1:02:24It has nothing to do
1:02:26with the previous output. So, the
1:02:28combinational logic is memoryless. So,
1:02:30output determined by current values of
1:02:33the inputs only.
1:02:34And there is also another concept, it is
1:02:36sequential logic. Sequential logic has
1:02:38memory. It has a memory inside and it
1:02:41keeps a state. And outputs depend on the
1:02:44input and state at the same time in
1:02:46sequential logic.
1:02:48So, outputs determined by previous and
1:02:50current values of inputs.
1:02:54You should be familiar, by the way,
1:02:56with these concepts because it is a
1:02:59content I think related to a content in
1:03:01second class, the course you took in
1:03:03second class, second Yeah, second year.
1:03:07Uh
1:03:07In here, you can see a summary of the
1:03:09combinational logic gates. Uh there are
1:03:11inversion, NOT, AND, OR, NAND, NOR
1:03:15uh gates.
1:03:17Single input ones are not gate and
1:03:20buffer and two input ones are and or
1:03:22exor nand nor exnor. And there are
1:03:24multiple input ones also.
1:03:27Uh, so for example, you can build five
1:03:28input and gates also. It is
1:03:31you can do it.
1:03:32Uh, and also
1:03:35the three-state buffer is also two input
1:03:37gate because it has a
1:03:38two two inputs, enable and input.
1:03:42And you can also, for example, build a
1:03:45two to one mux by using these logic
1:03:48gates.
1:03:49Uh, you can see all their look up tables
1:03:51in here.
1:03:56Yeah, you you need to be familiar with
1:03:57these concepts, but of course you might
1:04:00be forgetting them since maybe
1:04:02it was
1:04:04one one years before,
1:04:06uh, but you can review.
1:04:09So,
1:04:11more complex systems built on top of the
1:04:13fundamental gates. For example, in here
1:04:15I uh, here I have an example priority
1:04:17circuit. This priority circuit is
1:04:19actually just look at this input
1:04:23and it gives one
1:04:27in the corresponding output,
1:04:29depending on the input. For example, in
1:04:31here
1:04:32in the input, if A3 is one, it says that
1:04:37this A3 is one, so it makes Y3 one and
1:04:40other zero.
1:04:42And it doesn't matter what the other A2
1:04:45A1 A0 is one or zero.
1:04:49So, whenever A3 is one, it gives Y3 as
1:04:52one, but if A3 is not one,
1:04:56it selects the one
1:04:59uh, with highest actually most
1:05:01significant one.
1:05:03So, this Y output actually shows the
1:05:06corresponds to the digit that is the
1:05:09most significant and it is one.
1:05:11Okay, this is the priority circuit. You
1:05:13can understand it by looking this uh
1:05:16look up table.
1:05:17Uh in this look up table, this one is
1:05:19the inputs and this one is the outputs.
1:05:23So, whenever, for example, A3, A2, and
1:05:26A1 is zero,
1:05:29in this case, Y0 is one if A0 is one. If
1:05:33it is zero, is A0 is zero.
1:05:37But, for example, whenever A2 is one,
1:05:41and A3 is zero,
1:05:44these values doesn't matter. It gives it
1:05:47signals Y2 as one.
1:05:49Because the most significant one in the
1:05:52circuit is A2, so A2 corresponds to Y2.
1:05:56So, there's a direct correlation between
1:05:58them.
1:05:59So, if the most significant bit is A3,
1:06:02one, then Y3 becomes one. If it is A2,
1:06:06Y2 becomes one. If it is A1, Y1 becomes
1:06:08one.
1:06:10So, how can we design such a circuit? Uh
1:06:13we are using AND OR gates by design such
1:06:16a circuit. There are methods, I will not
1:06:19show these methods,
1:06:20uh but, for example, when you look at
1:06:22this
1:06:23look up table,
1:06:25uh truth table,
1:06:26uh Y3 actually is corresponding directly
1:06:29to A3. Whenever A3 is one, Y3 is also
1:06:32one. So, we can say that Y3 is equal to
1:06:35A3.
1:06:36So, Y3 is directly connected to A3.
1:06:39What about Y2?
1:06:41Y2 is one only if A2 is one and A3 is
1:06:44not one. Because if A3 is one, then it
1:06:48means that Y3 is one, because the most
1:06:50significant one is A3.
1:06:52So, it's corresponding
1:06:54logic equivalence is A3 not times A2.
1:06:59And this is for Y1 and this is for Y0.
1:07:01So, this is compared to basic logic
1:07:05gates, this is more complex circuitry
1:07:07because it is priority circuit.
1:07:09And we are building it by using this
1:07:12NAND gates.
1:07:14We can build it.
1:07:15These are the primitive gates and
1:07:17combining with these primitive gates, we
1:07:19are building more complex circuitry and
1:07:22by bring by using this
1:07:24a little bit complex circuitry and we
1:07:26are building much more complex circuitry
1:07:28and at then we are designing very
1:07:31complex high performance processors. For
1:07:33example, priority circuits are
1:07:35very widely used in an out of order
1:07:38processor.
1:07:41But of course, we as I told you, we are
1:07:42not
1:07:44designing by combining the transistors.
1:07:46We will design it by writing hardware
1:07:48description language and in this class
1:07:50also I will mention about I will teach
1:07:52you hardware description languages,
1:07:54which is a System Verilog.
1:07:57So, what about sequential logic gates?
1:07:59In sequential logic gates, outputs of
1:08:01the sequential logic depend on the
1:08:02current and prior input values if it has
1:08:05a memory.
1:08:07Uh
1:08:08so, it has a memory by the way. Uh
1:08:11there are some definitions in here.
1:08:13State is the information
1:08:15uh kept inside a circuit inside the
1:08:17circuit in sequential logic circuit.
1:08:21And we can keep the state in latches and
1:08:23flip-flops. They are named as state
1:08:25elements.
1:08:26Uh they store one bit of state.
1:08:29And synchronous sequential circuits are
1:08:31the sequential circuits using flip-flops
1:08:33sharing a common clock.
1:08:36So, the most basic actually in here,
1:08:39okay, I mentioned about state. Uh
1:08:42state is like a
1:08:44state of the circuit. It's like memory.
1:08:46Okay, the the
1:08:48in sequential logic gates, circuit has a
1:08:50memory.
1:08:52And it keeps a state in this memory.
1:08:55And in order to keep it as for memory,
1:08:58we are using latches and flip-flops.
1:09:01And in here, we have a basic memory.
1:09:07We know gates, okay? In In gates, we are
1:09:09applying some input and getting an
1:09:11output. But, how we should keep a logic
1:09:14value?
1:09:17How can we design a memory element that
1:09:19keeps the value?
1:09:22In the most basic methodology, we can
1:09:25design it by using cross-coupled
1:09:27inverters.
1:09:28So, in here, I have an inverter and
1:09:31another inverter. They are connected to
1:09:32each other.
1:09:34So, this is same connection topology, by
1:09:36the way.
1:09:38So, in here, when we cross-couple an
1:09:41inverter, it keeps the value. For
1:09:43example, think that
1:09:45this is two inverters.
1:09:47Think that, for example, I have a one in
1:09:50here
1:09:52and zero in this Q in this Q output. And
1:09:56the zero in this Q output feeds zero to
1:10:00second inverter. And this second
1:10:02inverter gives one in Q bar in Q not.
1:10:06And this one
1:10:08is already one in here.
1:10:09So, if I don't interfere the circuit,
1:10:13it keeps this value. For example, if
1:10:16there is a Q is zero, for example, it
1:10:18keeps zero to here. Because, by the way,
1:10:20these are VDD and VSS connections. They
1:10:23are not shown generally.
1:10:26But, this keeps this value.
1:10:28Just four transistors. By using just
1:10:30four transistors, we can keep single
1:10:32value.
1:10:33So, whenever If I want to change this
1:10:35value, I can apply zero to here, and
1:10:37this zero flips everything.
1:10:40Flips this one, and this flips this one,
1:10:42and in here, starting from after
1:10:44applying this zero, this Q gives one.
1:10:47But, if I don't touch this circuit, it
1:10:49keeps this value, right? This coupled
1:10:51inverters keeps this value. This is the
1:10:53most basic memory
1:10:55that we can use in in sequential logic
1:10:59gates.
1:11:02But people are designing better ones.
1:11:04One of them is SR latch.
1:11:07This is the most basic one.
1:11:09Cross-coupled inverters, but it has only
1:11:11inputs. But people are designing more
1:11:13complex one, more useful ones. One of
1:11:15them is SR latch.
1:11:17People build SR latch by using NOR gates
1:11:21in a similar way
1:11:23in a similar way to the inverters.
1:11:25People cross-couple the NOR gates in
1:11:28this way.
1:11:30And now it has two inputs.
1:11:33R input for reset and S input for set.
1:11:37And in this circuit you can do it
1:11:40you can try it in in in home. Whenever
1:11:43you apply
1:11:44one to R
1:11:46it gives zero
1:11:48at this Q output. Whenever you apply one
1:11:51to S, it gives one in here.
1:11:55So, in order to reset it, reset means
1:11:57that you are setting Q as zero, you can
1:12:00apply one to R R input. And in order to
1:12:04set it, you can apply one to S input.
1:12:08And whenever S is zero and R R is zero,
1:12:11it keeps this value. So, Q keeps the
1:12:14previous value of Q. So, it keeps the
1:12:15value.
1:12:18In this SR latch, you shouldn't by the
1:12:20way, there is a forbidden input
1:12:22combination. You shouldn't apply S one
1:12:27and R one at the same time.
1:12:29Because if you apply S one and R one at
1:12:32the same time, you don't know the output
1:12:33value. It is unknown. It's for For this
1:12:36reason, it is forbidden state.
1:12:38So, SR latch is more useful one because
1:12:40you have R and S inputs. So, if you want
1:12:43to set it, you only can apply one to S
1:12:45input. And if you want to reset it, you
1:12:47want to apply one to R input.
1:12:50And people use this SR latch
1:12:53to build a D latch.
1:12:57Uh
1:12:57By the way, yeah, you can use D latch SR
1:13:00latch to build a D latch, but in here
1:13:02there is a different methodology to
1:13:04build a D latch.
1:13:05In this D latch, we have a clock input.
1:13:10This clock is can be zero and one.
1:13:12But whenever clock is one,
1:13:15if you apply a D input to this D input,
1:13:20it stores this value in here in SR
1:13:23latch. Yeah, here is SR latch.
1:13:27Uh yeah, in here we we used SR latch to
1:13:29build it, okay?
1:13:31We used SR latch to build a D flip flop
1:13:34D latch. So, in this D latch, whenever
1:13:37clock comes here,
1:13:39this here is SR latch part.
1:13:42But in front of the SR latch, I am
1:13:44putting AND gates,
1:13:46and this AND gate is actually prevents
1:13:50us from this state,
1:13:52applying S and R one at the same time.
1:13:54It prevents.
1:13:56And in this
1:13:58AND gates,
1:14:00we connected a clock input and D input,
1:14:03and not of D goes to this AND gate, and
1:14:07the functionality is as follows.
1:14:09Whenever this clock is one,
1:14:11whenever clock is one,
1:14:13D passes its input to this SR latch, so
1:14:17this SR latch stores this D. But
1:14:20whenever this clock is zero, it it keeps
1:14:23the value that it has stored in here.
1:14:27It holds the its previous value.
1:14:29So, whenever clock is one, it is
1:14:31transparent. Transparent means that D is
1:14:34goes
1:14:35to here, and whenever clock is zero,
1:14:38it is opaque. It means that it doesn't
1:14:40pass this D to
1:14:42SR latch.
1:14:45And this clock is
1:14:47you can think it as an enable. Whenever
1:14:50enable is one,
1:14:51it stores the D in here. Whenever enable
1:14:53is zero, it doesn't store anything. So,
1:14:56it keeps its previous value.
1:14:59And by using this
1:15:01Okay, this were the latch.
1:15:03Okay?
1:15:05And I told that there are latches and
1:15:08flip-flops.
1:15:10Flip-flops are a little bit different
1:15:12than latches.
1:15:14Uh and we can build a flip-flop by using
1:15:17two
1:15:19latches, two D latches.
1:15:24In here,
1:15:25we have two D latches. They are two
1:15:27latch D latches, two D latches.
1:15:30And we are connecting a clock to them.
1:15:33You can think clock as enable, okay?
1:15:38Whenever this clock
1:15:41is
1:15:42becoming one,
1:15:45this D is sampled in here.
1:15:47Whenever this clock is zero
1:15:51or not moving,
1:15:52there is nothing stored in here.
1:15:56Uh maybe I can mention about Yes, I can
1:15:58mention about the functionality
1:16:01how it is behave so.
1:16:04I I'm I mentioned about the latch,
1:16:06right? So, latch says that whenever here
1:16:09is one, it passes
1:16:11this D and stores it in here.
1:16:14Whenever this clock is one, it
1:16:16this stores
1:16:18the value at the D input inside the SR
1:16:20latch, okay?
1:16:23This
1:16:24flip-flop is uh
1:16:26behaves a little bit differently. Uh
1:16:30In the previous case,
1:16:34for example, we can generate a clock
1:16:36signal. This is a clock signal.
1:16:39This latch was sampling this D input
1:16:42while clock is one.
1:16:45But in flip-flop, we can draw a clock
1:16:48again.
1:16:50This flip-flop, this is a flip-flop.
1:16:53This flip-flop stores the value at D at
1:16:56the rising edge of the clock. How?
1:17:00I can go because this is a D flip-flop,
1:17:03by the way.
1:17:04This is a D flip-flop. This is a
1:17:06corresponding symbol of it.
1:17:09So,
1:17:11this is the This is my clock signal.
1:17:14And Q is our
1:17:16corresponds to value stored, okay? Well,
1:17:18this is the value stored.
1:17:20Whenever clock is rising, think for
1:17:24example, at the beginning, clock is
1:17:26zero, okay? If clock is zero,
1:17:29this zero goes to this latch as one
1:17:32because there is an inverter in here.
1:17:34So, clock zero means that this latch
1:17:37gets the clock as one because it it
1:17:39takes the not of the clock.
1:17:41So, whenever this clock is one,
1:17:44this SR latch samples D in here. So,
1:17:47this Q corresponds to D and one. The N1
1:17:51corresponds to D. It keeps the D value,
1:17:54okay?
1:17:55But at the same time, the clock in here,
1:17:58it is a directly connected to clock.
1:18:00This clock input is connected to
1:18:02directly clock. It is zero. So, it
1:18:04doesn't pass through here. It doesn't
1:18:07pass through here. So, Q keeps the
1:18:09previous value because whenever clock
1:18:11was zero in latch, it was giving the
1:18:12previous value.
1:18:15Okay?
1:18:16So,
1:18:17at this point,
1:18:19in here, the first latch sampled this D
1:18:22value,
1:18:24but it is in here between two latches in
1:18:28in this N1 value.
1:18:30So, whenever this clock goes from zero
1:18:32to one,
1:18:34in this case, clock goes zero to one. It
1:18:38means that here is becoming zero, here
1:18:41is becoming one.
1:18:43If here becomes zero, this connection is
1:18:46closed, right?
1:18:48This D is stored in here, and when this
1:18:52clock becomes one, at that time, this D
1:18:55passes to here
1:18:57while this clock becomes zero to one.
1:19:00This value at the previous value at the
1:19:03N1 location passes to this second latch,
1:19:07and Q corresponds to D.
1:19:10So, in this case, we can say that
1:19:13while clock is rising, this flip-flop
1:19:15sampling. Did Did you understand it? Can
1:19:18You understand, right?
1:19:20Because this this latch works while
1:19:22clock is zero sample clock is zero, and
1:19:25this latch samples while clock is one.
1:19:27So, while switching from zero to one,
1:19:30this value passes to here, and it
1:19:32samples It means that it samples while
1:19:35at the rising edge of clock.
1:19:37So, in latch,
1:19:40we are sampling at the edge of the
1:19:42clock.
1:19:43Uh
1:19:44sorry, not at at the level.
1:19:47If clock is one or zero. By the way,
1:19:49there are reverse latches. For example,
1:19:51you can get the inverse of it. You can
1:19:54sample at zero. It is It is You can do
1:19:56it in this way. But generally speaking,
1:20:00in latch,
1:20:01you sample at the level.
1:20:04And in D flip-flop in flip-flops, you
1:20:06sample at the edge.
1:20:09At the edge.
1:20:11Uh By the way, maybe until now,
1:20:14maybe in the last four five years, I
1:20:16interviewed maybe around 500
1:20:19uh electrical electronics engineering
1:20:21students, and maybe 90% of the students
1:20:23didn't know it. Didn't know the
1:20:25difference between the latch and
1:20:26flip-flop.
1:20:29According to the statistic that I got
1:20:31from my interviews, job interviews. So,
1:20:34this is a important concept for
1:20:36logic digital design.
1:20:39Latches sample at the edge at the level.
1:20:42So, they are level triggered and
1:20:44flip-flops samples at the edge.
1:20:47And we are using clock for to generate
1:20:49the enable signals actually. Clocks are
1:20:51at the enable signals.
1:20:54So, here is a description.
1:20:59So, when clock is zero, so that's that
1:21:02what I mentioned to you.
1:21:05Okay.
1:21:07And by using these
1:21:10flip-flops, we are building finite state
1:21:12machines. You have to be familiar about
1:21:14them. And there are two finite state
1:21:16machines, Moore and Mealy FSM finite
1:21:19state machines.
1:21:21Uh
1:21:21these are used to to keep the states.
1:21:24And in this finite state machines,
1:21:27depending on the input, our state is
1:21:29changing.
1:21:30Uh and a finite state machine consists
1:21:32of
1:21:33two
1:21:35parts. One of them is a state register
1:21:36that keeps the current state.
1:21:39And other one is the combination logic.
1:21:41It depends combination logic computes
1:21:43the next state and also computes the
1:21:45output at the same time.
1:21:49Uh by the way, a complex processor is
1:21:51also a finite state machine. In digital
1:21:54design,
1:21:56uh everything nearly, if you are using a
1:21:58flip-flop to keep state, everything is
1:22:02we can say that everything is a finite
1:22:03state machine.
1:22:05And in this finite state machine, next
1:22:06state is determined by the current state
1:22:08and inputs.
1:22:11There are two types of it, Moore and
1:22:13Mealy. Uh
1:22:15actually, we don't care much Moore or
1:22:17Mealy. While designing the complex
1:22:19processors, we are writing hardware
1:22:21description languages for this. We don't
1:22:23care much whether it is Moore or Mealy.
1:22:25we don't care it.
1:22:39I will briefly mention about also timing
1:22:41and power.
1:22:43Combinational logic gates has timing
1:22:47because signal travels. So, how signal
1:22:50travels?
1:22:51For example, when you apply a signal
1:22:54to here,
1:22:56it is not like light.
1:22:58For example, when you apply a logic one
1:23:00to here, it doesn't goes to be
1:23:02immediately because it is not just a
1:23:04wire. It is when you look at it,
1:23:07actually there is a resistor in here and
1:23:09there is a capacitor in here.
1:23:11These are named as parasitics.
1:23:14So, in order to For example, if we apply
1:23:17a one logic one to here, in order to get
1:23:20a one in B, we have to fill this
1:23:23capacitor. So, that this capacitor at
1:23:25the output it gives to be
1:23:28the value to be.
1:23:29So, it takes time to fill this capacitor
1:23:32because electrons are moving
1:23:35and these electrons fills this capacitor
1:23:37and whenever this capacitor fills, this
1:23:39B gets one. But, it's very fast by the
1:23:41way, yeah. For example, in
1:23:43in 16 nanometer technology, if you are
1:23:45using an AND gate,
1:23:46uh delay is maybe 5 picosecond. It is
1:23:49very fast.
1:23:51But, there is there are delays. And in
1:23:54combinational logic gate, uh for this
1:23:56reason, there is a concept of critical
1:23:58path. Critical path corresponds to path
1:24:02that is the slowest one.
1:24:07For example, in here, I have a D. Uh
1:24:10this D input just goes this AND gate and
1:24:13goes to Y output, changes the Y output.
1:24:16This is a very fast path.
1:24:18But, corre- when you look at the path
1:24:20between A and Y, this path is goes loss
1:24:24of gates in and in each gate there are
1:24:28parasitics.
1:24:30Resistor and capacitor. So, while going
1:24:33through each gate
1:24:35time passes.
1:24:36So, this is the critical path, for
1:24:38example. In here, most likely this is
1:24:39the critical path. It doesn't We don't
1:24:41know. We need to use
1:24:43synthesis tools. This is the By the way,
1:24:48implementation
1:24:49actual implementation of the integrated
1:24:51circuit is the uh
1:24:56Uh but, of course, you need to do
1:24:58implementation and look at the result.
1:24:59But, most likely this is the critical
1:25:01path in here. So, critical path means
1:25:04that when you apply a signal to here,
1:25:07and this signal, the change in this
1:25:09signal
1:25:10reflects to here, uh
1:25:13but it takes time, more time compared to
1:25:16other ones. It is the longest path.
1:25:19When you look at this path, for example,
1:25:21the critical path in here from between A
1:25:24and Y, it corresponds to two AND gates.
1:25:28Two AND gates.
1:25:30Uh
1:25:31This is first AND gate, this is second
1:25:34AND gate, and one OR gate. It takes the
1:25:37two It needs to pass through two AND
1:25:38gate and one OR gate. And when you look
1:25:40at the short path, it needs to go
1:25:43through one AND gate.
1:25:45And there are concept of max and min
1:25:46delay.
1:25:49So, in here, the important thing is that
1:25:54for example, since
1:25:58you don't know, for example, inside
1:26:00while driving this circuit, for example,
1:26:02you are driving some input to here and
1:26:04getting some output to here,
1:26:07since you don't know which input is
1:26:09changing,
1:26:10you have to set your circuit operating
1:26:13frequency
1:26:14regarding the longest path.
1:26:16That's why, for example, people are
1:26:18saying that our processor is working at
1:26:212 GHz. It means that the critical path
1:26:23inside the this processor
1:26:26uh corresponding to 0.5 ns.
1:26:29Because 0.5 ns means that 2 GHz.
1:26:32>> Mhm.
1:26:32>> So,
1:26:34by the way, the critical path
1:26:36decides on the maximum running
1:26:38frequency.
1:26:43In here, there are some called steps in
1:26:45combination logic gate timing.
1:26:47Uh delay, as I told you, it is the time
1:26:49between input change and output change.
1:26:52Uh there are two types of delays,
1:26:54propagation delay and contamination
1:26:56delay. Propagation delay is actually
1:26:58maximum delay.
1:27:00And contamination delay is the minimum
1:27:01delay. So, in here, for example,
1:27:04propagation delay, we can say that, for
1:27:06example, the maximum of this one and
1:27:09contamination is the minimum.
1:27:11From D to Y is the contamination, A to Y
1:27:13is the
1:27:15uh maximum one.
1:27:18But, it is not always the input and
1:27:20output paths. Sometimes, even, for
1:27:23example, you have a gate, for example, A
1:27:25and B, and you have a output in here.
1:27:29For example, maybe this A to Y change is
1:27:31faster than B to Y change. So, in this
1:27:34case, B to Y is the maximum delay, A to
1:27:37Y is minimum delay.
1:27:40And even sometimes, for example, think
1:27:43you have a single buffer.
1:27:46And it has a single input and single
1:27:48output.
1:27:49It has a simple concept of mean and max
1:27:52delays.
1:27:53How?
1:27:54Uh because it change some with uh PVT.
1:27:59Uh
1:28:00PVT means that process, V means voltage,
1:28:03T means temperature.
1:28:05Uh process,
1:28:07don't worry about process.
1:28:09It is the
1:28:11topic of the next course. But, for
1:28:12example, sometimes as I told you, it is
1:28:15not exactly VDD. It is maybe 0.8 0.
1:28:19between 0.8 and 0.7.
1:28:22So, if for example, this
1:28:24voltage, for example, applied voltage to
1:28:27this buffer is 0.7 V,
1:28:30this gate is a little bit slower because
1:28:33it is voltage is less than the nominal
1:28:35one. So,
1:28:37if it is 0.8, it is faster.
1:28:40So, still
1:28:42there is a even if there is a single
1:28:45input, there is a range
1:28:48between min and max, and we need to care
1:28:50about it still. For example, for this
1:28:53buffer
1:28:55A,
1:28:56whenever we apply an input to here, for
1:28:58example, we apply an input in here. We
1:29:01applied a new input at this point,
1:29:04and it takes some time
1:29:06to be reflected at the Y point.
1:29:09So, and it has a subtle minimum and
1:29:12maximum delays.
1:29:15So, the minimum one is that, for
1:29:18example, you apply a input to A, you
1:29:21change the input at the A, maybe minimum
1:29:23is 1 nanosecond, it change after 1
1:29:25nanosecond, and maximum is
1:29:282 nanosecond.
1:29:30So, it can be the earliest one
1:29:33is after 1 nanosecond, and latest one is
1:29:35after 2 nanosecond. So, it can be any
1:29:38time between 1 nanosecond and 2
1:29:40nanosecond, but not between before 1
1:29:43nanosecond and after 2 nanosecond.
1:29:45So, it has a still concept of
1:29:48minimum and maximum delay even if it is
1:29:51a single input.
1:29:52And this is very important. Why it has a
1:29:55minimum and a maximum? Because the
1:29:57voltage changes in here. While, for
1:29:59example, you connected billion of
1:30:01transistors, some of them getting 0.8
1:30:040.8 V, some of them is getting 0.75
1:30:07volts. Some of them is getting 0.78
1:30:10volts. It changes. Temperature also
1:30:12changes. In your IC, for example, some
1:30:15place of the IC is 85 degree, some
1:30:17places 84 degree. The even these
1:30:20temperature differences create small
1:30:22differences between this delay. For this
1:30:24reason, while designing designing the
1:30:28logic digital designs, we have a concept
1:30:30of minimum and maximum delays always.
1:30:34And this delay is caused also by
1:30:35capacitance and resistance in a circuit,
1:30:38not only PVT.
1:30:40PVT is important. By the way, process is
1:30:43the quality of the transistor. Sometimes
1:30:46transistor quality is not good. So, at
1:30:48that time P corresponds to process, by
1:30:50the way. At that time
1:30:52the for example, NMOS transistor is
1:30:55maybe or or under function.
1:30:57Less performance, providing less
1:30:59performance.
1:31:01It
1:31:02delay is caused by
1:31:03uh PVT. Delay differences caused by PVT
1:31:06and also capacitance and resistance
1:31:08causing the delay also.
1:31:10So, why we have a
1:31:12propagation and contamination concepts
1:31:15uh because
1:31:17yeah, PVT differences. And also another
1:31:20one that I mentioned about.
1:31:23For example, this A is changing in here.
1:31:25This also another another stuff that
1:31:28leads to different propagation and
1:31:30contamination delay. If you drive this A
1:31:33very sharply,
1:31:34then you get very fast response in here.
1:31:36But what about if you drive it very
1:31:38slowly?
1:31:40You are getting
1:31:41slower response at Y. Also, it also
1:31:44changes
1:31:45how sharply apply this A input to here.
1:31:49And most likely this A input is output
1:31:51of another gate. And if this gate drives
1:31:53it sharply,
1:31:55Y also gives the output very fastly. But
1:31:58if it doesn't, Y Y is also slower.
1:32:03And also multiple in outputs I mentioned
1:32:05that in here there are multiple inputs
1:32:07and outputs and each of them has a
1:32:09different delay.
1:32:11And circuits slow down generally when
1:32:13hot and speed up when cold.
1:32:16Yes.
1:32:19Process voltage temperature TVT.
1:32:22Process how the trans quality of the
1:32:24transistor
1:32:25while manufacturing because you are not
1:32:27getting there are billion of transistors
1:32:29and you are not getting the same quality
1:32:31quality every time.
1:32:33And temperature is the actual
1:32:34temperature.
1:32:36It changes inside a processor.
1:32:38Temperature is different in the in the
1:32:41die. Die means IC by the way.
1:32:44And voltage is also different.
1:32:50And the there are in this is for the
1:32:53combinational logic gate timing.
1:32:56And in sequential
1:32:58logic circuits especially for flip-flops
1:33:00there are also some timing
1:33:02knowledge.
1:33:04But maybe
1:33:08is it better to give a break, right? We
1:33:10we started at 50
1:33:12and now it is okay. We we can give a
1:33:13break maybe 15 minutes break and then
1:33:16continue.
1:33:19We can we can start at 55.
1:33:41So related to sequential circuits
1:33:44flip-flop timing
1:33:46flip-flop samples at D samples D at
1:33:49clock edge and D must be stable while
1:33:51sampled.
1:33:52So
1:33:53the point in here is that
1:33:56for example I told you that while clock
1:33:58is
1:34:00clock is rising
1:34:02while clock is rising, this flip-flop
1:34:06is sampling this D.
1:34:09But, what if D changes
1:34:11in here while sampling?
1:34:14This is a timing violation because there
1:34:17are some rules in here you need to obey.
1:34:21And these rules are summarized as setup
1:34:23time and hold time.
1:34:25Uh setup time is the time before clock
1:34:28edge data must be stable. So, it's you
1:34:31can think at it as a taking photograph.
1:34:34For example, while running if you take a
1:34:36photograph, your picture will not be
1:34:39clear.
1:34:42So, while taking a photograph
1:34:44photograph, you must be you must be
1:34:47stable actually. You you shouldn't move.
1:34:50And
1:34:51also while taking for example, it
1:34:54sampled you the photograph
1:34:56the photograph machine sampled you, also
1:34:58you need to keep stable a little bit
1:35:00more because while sampling it's is
1:35:03it's still sampling, so you have to be
1:35:05you have to be stable.
1:35:08And you can think the setup and hold
1:35:10time in a similar way.
1:35:12While sampling, the setup time is the
1:35:14time
1:35:15before sampling, you have to be stable.
1:35:18The input at the D must be stable.
1:35:21And hold time is the time after clock
1:35:25edge after this clock edge you have to
1:35:28keep the D stable.
1:35:31So, you have to be stable before the
1:35:33clock edge and you have to be stable
1:35:35after the clock edge also.
1:35:39If you change the D input during this
1:35:42period, during this interval we don't
1:35:44know what is stored in flip-flop. This
1:35:47is the violation of timing. We don't
1:35:48know. In this case, the circuit doesn't
1:35:50behave correctly.
1:35:53The setup time is the time before the
1:35:56clock edge it must be stable and hold
1:35:58time is the time after the clock edge it
1:36:01must be stable. Input must be stable and
1:36:03aperture time is the
1:36:06the combination window of setup and hold
1:36:08time. So during that time uh
1:36:11the during the aperture time the D must
1:36:14be stable.
1:36:15It is the combination of setup and hold
1:36:17time.
1:36:18And in here also the similar similar to
1:36:21the
1:36:22the
1:36:23combination logic gates we have a
1:36:24propagation delay and contamination
1:36:26delay concepts still. Propagation is the
1:36:29maximum delay, contamination is the
1:36:30minimum delay.
1:36:32The
1:36:33propagation delay the T propagation
1:36:36clock to Q. It means that
1:36:41this
1:36:42uh D input
1:36:43it means that time after clock edge that
1:36:46Q is guaranteed to be stable
1:36:49to stop changing. Means that for example
1:36:51you have a flip-flop, okay?
1:36:54You have a D input in here and Q
1:36:57output in here and when clock comes you
1:36:59are sampling this D, right? And this D
1:37:02must be stable during aperture time.
1:37:05It means that setup and hold time. Setup
1:37:07plus hold time.
1:37:09And also it takes some time to
1:37:13to take the D and pass it to to Q
1:37:17because in here there are gates, right?
1:37:19These gates must
1:37:21forward the signal.
1:37:22And
1:37:24the clock comes and the
1:37:27change at the D reflects to Q.
1:37:31During that time the time that passes
1:37:32named as propagation delay, but this is
1:37:34the maximum of it.
1:37:36So
1:37:38when this clock comes
1:37:42the Q
1:37:44output change depending on this D input
1:37:47and this time the maximum of it is named
1:37:50as propagation, and minimum of it
1:37:53contained as contamination. So, there
1:37:55are two versions. Maximum clock to Q
1:37:58delay. This CQ means that clock to Q
1:38:00delay.
1:38:02So, when clock comes
1:38:05to reflection on the Q takes time. So,
1:38:07there is a maximum and minimum of it.
1:38:10So, when you look at it,
1:38:13when you look at this flip-flop diagram,
1:38:17the input in here, it must be stable
1:38:21before the clock edge, at least T setup
1:38:23time, and it must be it must be stable
1:38:25after the clock edge during this T hold
1:38:27period, and the combination of these two
1:38:30period is named as aperture time.
1:38:33And propagation delay means that after
1:38:36this clock comes, when this clock rises,
1:38:39we are sampling this a D, right? Okay,
1:38:42there is a D input in here, and we are
1:38:44sampling it.
1:38:46And there is a time.
1:38:47The maximum time is the propagation
1:38:50time, minimum one is the contamination
1:38:52time, and it changes.
1:38:54So, when clock comes, this D input
1:38:58is reflected to Q, output at Q.
1:39:02And earliest time
1:39:04you can see it at after contamination
1:39:07delay, and maximum you can see it after
1:39:09propagation delay, and between them.
1:39:12But,
1:39:14it is guaranteed that after in this
1:39:17point you cannot see it. It must become
1:39:20before propagation and after
1:39:22contamination, between them.
1:39:24It is guaranteed. Otherwise, we cannot
1:39:26build circuits. We need to [snorts] know
1:39:28these propagation delay and
1:39:29contamination delays.
1:39:31And this propagation delay and
1:39:33contamination delay are characteristic
1:39:35to flip-flop. They are given. If if they
1:39:36are designing a flip-flop, for example,
1:39:38we are using a flip-flop, Uh,
1:39:40we need to know its contamination and
1:39:42propagation delay. Then they give it to
1:39:44us.
1:39:46And also they are giving us the setup
1:39:48time and hold time. This is the specific
1:39:50to
1:39:51flip-flop.
1:39:53And while designing a digital circuit,
1:39:55we have to pay attention to them.
1:39:59I will show how we are
1:40:00using these values to compute our
1:40:03maximum frequency. I will show.
1:40:07What if we cannot pay attention to setup
1:40:09and hold time?
1:40:11Uh,
1:40:11it leads to metastability.
1:40:14Uh, so
1:40:15in here, basically I can mention here
1:40:18here there is a flip-flop and this is
1:40:20the inside of flip-flop. Uh, yeah, this
1:40:23is a
1:40:24correspondence of flip-flop. Actually,
1:40:27flip-flop is two latches.
1:40:30But people use the
1:40:32build a flip-flop by using inverters in
1:40:34here, right? And here there are pass
1:40:36gates.
1:40:38And in here I will I will try to explain
1:40:40how metastability in flip-flop happens.
1:40:43So, assume that clock is zero and
1:40:45becomes one.
1:40:47Clock, this is our clock signal.
1:40:50And
1:40:51I have a D value and I am trying to
1:40:53sample it to this D value.
1:40:56When clock is zero,
1:40:58this
1:40:59gate passes because this is if not if
1:41:03clock is zero, it means that clock is
1:41:05not one. So, clock not is one. So, this
1:41:08gate passes. Okay, this is the pass
1:41:10gate.
1:41:11This gate passes
1:41:14D to A.
1:41:16And this inverter, for example, assume
1:41:19that D is one. D is one. This inverter
1:41:23gives zero to here and this B
1:41:26uh, gives C zero and this D becomes one.
1:41:30Okay?
1:41:31And here is open. This since clock is
1:41:33zero, D here is open. Not con- not
1:41:35connected.
1:41:39So, after clock becomes one,
1:41:42this
1:41:44here is closed,
1:41:46here is opened,
1:41:49here is
1:41:51closed.
1:41:52O-
1:41:53Uh I mean, yeah, here is
1:41:54opened. Here is opened, also. It It
1:41:57means that it's passing.
1:41:59And this zero passes to here, and it
1:42:01gives one to here, and this one
1:42:04correspondingly gives zero to here. Here
1:42:05is closed, also. This is a basic
1:42:07flip-flop model.
1:42:12This uh Yeah, you can check it, but this
1:42:14is a basic flip-flop
1:42:16also built by inverter gates. Normally,
1:42:18I show you how to build flip-flop by SR
1:42:20latch, but this is the version with
1:42:22inverter gates. You can also build a
1:42:24flip-flop by using inverter gates. And
1:42:27these are the pass transistors.
1:42:29Actually, this one corresponds to AND
1:42:31gates. You can build them by using AND
1:42:32gates.
1:42:33But, the important point here is that I
1:42:35will mention about the importance of the
1:42:38setup and hold time. So, if clock is
1:42:41Assume that clock is zero, okay?
1:42:44And I have a D input
1:42:48in here, some D input.
1:42:53I have a setup and hold time
1:42:56setup and hold time
1:42:59margins in here.
1:43:01And I assume that
1:43:03this clock is zero. So, if this is zero,
1:43:07here is opened. So, D passes to A.
1:43:12Assume that D is at the beginning one,
1:43:15okay?
1:43:17And the circuit in here
1:43:21gets the samples the D at one. So, here
1:43:25is becoming
1:43:26one, here is becoming zero, here is
1:43:28zero, and here is one. Here is closed,
1:43:31okay?
1:43:35And
1:43:36during that time, assume that this D
1:43:39change in here very fastly.
1:43:42For example,
1:43:45assume that okay, I will change the D in
1:43:48here, okay? D change in here. D became
1:43:51one in after setup time.
1:43:53Okay?
1:43:55So,
1:43:58assume that D change after setup time.
1:44:00It means that it was zero before. D was
1:44:03zero before. So, if it is zero, here was
1:44:06be one. Here was
1:44:08uh one and here was zero, okay?
1:44:12If it is changed very close to the
1:44:16edge of the clock,
1:44:19assume that it change a little bit very
1:44:22later than this T setup, okay?
1:44:26So, assume that we we
1:44:28make the D one, okay? Here became D one.
1:44:32And
1:44:33if here is one, this B starts to be
1:44:36zero, okay?
1:44:38Because this clock was this this gate
1:44:40was closed, okay?
1:44:43But
1:44:44okay, it
1:44:46D was one.
1:44:47Since D one was one, this point B point
1:44:51starts to be zero. But it was one before
1:44:54and it starts it started to decrease to
1:44:57to zero.
1:45:00So, it was one, but it started to
1:45:02decrease to zero.
1:45:04Like zero. It was going to zero.
1:45:06But immediately, since I changed the D
1:45:09one
1:45:10very close to the edge of the clock,
1:45:12assume that clock changed and become
1:45:15one.
1:45:16So, immediately we close this gate.
1:45:19We close this gate. We open this gate.
1:45:21And it couldn't be zero exactly. It
1:45:24stayed between them, between one and
1:45:26zero. Did you see this point?
1:45:28Because it couldn't change because it
1:45:30was very close to edge of the clock and
1:45:32we couldn't charge enough to this B
1:45:34point. And the clock immediately changed
1:45:37and closed here, open
1:45:40closed here, opened here.
1:45:42And at that point we don't know the
1:45:44exact voltage in here. If we change the
1:45:47this D input
1:45:49after setup time window, we don't know
1:45:52this value. That's why people are
1:45:54putting setup and hold time constraints.
1:45:57Otherwise, we don't know the value at B,
1:45:59voltage at B.
1:46:01We we don't guarantee it.
1:46:04So, when we don't pay attention to this
1:46:06setup time, in this case we don't know
1:46:08the value at B. And if you don't know
1:46:10know the value at B, we don't know value
1:46:13at Q also. And it leads to
1:46:15metastability.
1:46:17So, this is the uh
1:46:21this uh
1:46:22measurement result.
1:46:24People put a flip flop. This is a flip
1:46:26flop. And assume that
1:46:29this is this is the
1:46:31uh
1:46:31in here I can draw a clock for you also.
1:46:34Assume that this is the clock.
1:46:37People are provided a clock to to this
1:46:40flip flop. This is the input on of this
1:46:43flip flop and this is the output of this
1:46:44flip flop.
1:46:47And assume that
1:46:49this flip flop has this time window.
1:46:51This is a T setup time window and this
1:46:54is a T hold time window.
1:46:57And we didn't pay attention to this T
1:46:59setup time and we changed this input
1:47:02after setup time.
1:47:05And people
1:47:06tried it maybe thousand times and this
1:47:08is the result.
1:47:10Maybe for half of them, this flip flop
1:47:12settles to one and for half of them, it
1:47:15settles to zero.
1:47:17So, we don't know the exact value. This
1:47:18is why people are putting paying
1:47:20attention while especially designing
1:47:23digital circuits, we pay attention to
1:47:25set up and hold times. Otherwise, we
1:47:26don't know what's happening to this
1:47:28flip-flop.
1:47:29And
1:47:31basically, this is set up and hold time.
1:47:33As I told you, set up time, you have to
1:47:35obey it, and it is the time before clock
1:47:38edge data must be stable. And hold time,
1:47:40time after clock edge data must be
1:47:41stable stable. And hold time is also in
1:47:45here, you can
1:47:46check the whole time concepts.
1:47:49Even after clock edge,
1:47:52after clock edge comes,
1:47:54if you change this D value,
1:47:57and if this D value change change passes
1:48:00through here, it also metastabilizes
1:48:02this Q value also again.
1:48:04So, that's why
1:48:06important even after clock edge,
1:48:09this D value shouldn't change. Okay,
1:48:12after clock edge, you can think that
1:48:13this is closed,
1:48:15but very close to this clock edge,
1:48:18it's still passing. It is not switching
1:48:21immediately. It is switching slowly,
1:48:23maybe in 5 picoseconds, 6 picoseconds.
1:48:26So, during that time, while switching
1:48:28this
1:48:29this transistors off, you shouldn't
1:48:32change the value also. This is also
1:48:34important. Otherwise, you can see a
1:48:36metastability in here.
1:48:38And this is the real
1:48:40oscilloscope results
1:48:42that results the metastability.
1:48:46So, we know the combinational circuit
1:48:49timing, sequential circuit timing. Now,
1:48:52we can do an example in here.
1:48:54In here, I have a
1:48:55circuit.
1:48:56I have a flip-flops in here.
1:48:59These flip-flops
1:49:01getting some inputs, and these
1:49:04at the rise of the clock,
1:49:06these inputs are given to here.
1:49:09And
1:49:12in here, we are doing some
1:49:14logic operations,
1:49:16and in the next clock edge, we are
1:49:18sampling the result of these
1:49:21logic gates in this flip-flops, okay? In
1:49:24here, we have a memory.
1:49:25This memory gets its value at this clock
1:49:28edge, and in the next clock edge
1:49:31we are doing some computations in here,
1:49:33and in the next clock edge we are
1:49:35sampling it.
1:49:39What's that?
1:49:45So, in here, I assume that we have
1:49:47flip-flops, and flip-flop has 60
1:49:49picosecond
1:49:50uh 60 picosecond setup time and 70
1:49:53picosecond hold time. So, it means that
1:49:56before the clock edge
1:49:5760 picosecond, in this interval we
1:50:00shouldn't change the input, and after 70
1:50:03picosecond of this clock edge, we
1:50:05shouldn't change the
1:50:07uh f- input of the flip-flop.
1:50:10And the basically, as I
1:50:13drove in here
1:50:16we have a clock. This clock actually is
1:50:18common. This is common clock.
1:50:21I drove this clock in here.
1:50:23In the first rising edge of the clock we
1:50:26are getting some input value from here,
1:50:29and these flip-flops stores this input
1:50:31value and gives this input value as the
1:50:33output also. And during that time, after
1:50:36getting the new input values to A B C D
1:50:39points at this location, we are doing
1:50:42some computations, logical computations
1:50:44in here. And then new results
1:50:47are
1:50:48sampled in the next
1:50:50flip-flop.
1:50:54So, here is
1:50:55Actually, people says that this is the
1:50:57launch.
1:50:58We are launching input, and this is the
1:51:01capture.
1:51:02We are launching input in here, and then
1:51:05in the next rising edge, we are
1:51:06capturing it. We are storing the result
1:51:08in here.
1:51:11So, I assume that setup time 60
1:51:12picosecond, hold time 70 picosecond, and
1:51:15for flip-flop maximum delay is 50
1:51:18picosecond. The clock to Q delay. And
1:51:21minimum is 30 picosecond.
1:51:23And for each gate, our logic delay is 35
1:51:26picosecond maximum and 25 picosecond
1:51:28minimum.
1:51:31So, when we look at here,
1:51:36when we look at here,
1:51:39uh
1:51:40the what is the maximum path in here?
1:51:43This is the maximum path. We are passing
1:51:45through three gates.
1:51:47And what is the maximum delay of these
1:51:48three gates? So, for gates, the maximum
1:51:52delay is 35 picosecond. So, when we
1:51:54compute it three times 35 picosecond,
1:51:56105 picosecond maximum delay.
1:51:59But also we had some constraints for the
1:52:03uh flip-flop.
1:52:05Assume that there is a flip-flop in here
1:52:08and another flip-flop in here, and we
1:52:10are doing some combinational logic in
1:52:12here.
1:52:15In the In this for this flip-flop, data
1:52:18must come before 35 picosecond sorry, 60
1:52:23picosecond setup window.
1:52:2560 picosecond setup window.
1:52:29So,
1:52:30we have 60 picosecond. Assume that this
1:52:33is a our clock period. So,
1:52:36this is period. One over period, by the
1:52:38way, one over period is the frequency.
1:52:41One over period is the frequency. So,
1:52:43the our clock period is the time between
1:52:46the clock edges.
1:52:48So, when you look at it for setup time,
1:52:50we can do a computation.
1:52:54We have three gates. So, three gates at
1:52:56105 picosecond gate delay, and we have a
1:53:01setup time constraint of 60 picosecond.
1:53:04And also I have a
1:53:07uh propagation delay.
1:53:10Maximum propagation delay, which is 50
1:53:12second 50 picosecond.
1:53:14So, this flip-flop gives 50 picosecond
1:53:17takes 50 picosecond. This
1:53:20because this takes 50 picosecond to come
1:53:22here from clock to Q.
1:53:24Here there is a 50 picosecond delay.
1:53:27This
1:53:28three logic gates gives 105 picoseconds.
1:53:3250 after 105 picoseconds and I have also
1:53:35in here a setup constraint that it must
1:53:38come before the uh 60 picosecond before
1:53:42the
1:53:43clock edge. So, when you look at the
1:53:44setup time constraint, 50 + 105 + 60
1:53:50what 215 picosecond setup time
1:53:53constraint. So, it means that this path
1:53:55takes
1:53:57255 picoseconds
1:54:01this way. So, it means that
1:54:05our maximum
1:54:06uh by the way, our minimum period is 215
1:54:0915 picosecond. So, when you compute the
1:54:13frequency by using it, uh
1:54:15it means it corresponds that uh this
1:54:18circuit can can work at 4.65 GHz GHz.
1:54:23It is one over period. It is frequency.
1:54:26So, it is 4.65 GHz it can run.
1:54:30How we are finding it? We are
1:54:32combining the delays maximum delays to
1:54:35find the maximum frequency. We are
1:54:37looking to the slowest path
1:54:39and we are combining the
1:54:41uh maximum delays and also we are taking
1:54:44the setup time constraint into
1:54:46consideration because the input must be
1:54:48ready before setup time. That setup time
1:54:50was 60 picosecond.
1:54:52So, the total path 215 picosecond and it
1:54:55corresponds to 4.65 GHz.
1:54:59What about hold time?
1:55:01Hold time looks to the
1:55:03shortest path, fastest path.
1:55:06So, what about the fastest path?
1:55:09Hold time,
1:55:11to recap, hold time says that
1:55:16in this flip-flop, in the rising clock
1:55:19edge, okay, there is a setup time
1:55:20constraint.
1:55:22The data must be ready before the rising
1:55:25edge of the clock at least by setup
1:55:27time.
1:55:28And after this rising edge, data must be
1:55:33stable. New data should not come
1:55:36during this T hold period time.
1:55:39So, for example, for this flip-flop,
1:55:42if this path
1:55:44after this
1:55:46flip-flop rises
1:55:48and while it is sampling the data at
1:55:51here,
1:55:53this flip-flop, this path shouldn't
1:55:55drive any data
1:55:58before this T hold time.
1:56:01Because while sampling this one,
1:56:04T hold means that after the rising edge,
1:56:07data must be stable. But after rising
1:56:10edge, if this data changes so fastly,
1:56:12very fastly, then it's still problem. It
1:56:15leads to metastability.
1:56:17So, for set hold time, we are looking to
1:56:20do fastest path and we are taking to the
1:56:24fastest
1:56:26timing
1:56:27uh values. So, what about the fastest
1:56:30timing values?
1:56:31There is a This is the fastest path, by
1:56:33the way.
1:56:34And this is a one and not NOR gate. And
1:56:38for this NOR gate,
1:56:40I am taking the fastest
1:56:43uh
1:56:45Sorry, not this one. I am taking the
1:56:47fastest
1:56:48uh contamination delay,
1:56:50minimum delay. So, it is 25 picoseconds.
1:56:54This is the fastest response time of
1:56:57this gate. I'm
1:56:59This time in while competing the setup
1:57:00time, I took the 35 picosecond maximum.
1:57:03But while
1:57:05competing the whole time requirement, I
1:57:07need to take the minimum because hold
1:57:09time uh
1:57:10is caused uh due to the fastest path.
1:57:14Because after flip flop rises, if new
1:57:17data comes very early,
1:57:20this is the whole time violation. So, I
1:57:22need to check this case and in order to
1:57:24check check this case, I need to look at
1:57:26the minimum time. So, for the the
1:57:28minimum one, it is 25 picosecond plus
1:57:31our whole time constraint,
1:57:33uh
1:57:34which is
1:57:35uh whole time constraint is uh where is
1:57:37it?
1:57:38Uh whole time constraint is 70
1:57:39picosecond, by the way. Yeah. This 25
1:57:42picosecond minimum delay and also for
1:57:45this flip flop minimum contamination
1:57:48clock to Q minimum delay 30 picosecond.
1:57:51So, 30 picosecond plus 25 picosecond 55
1:57:5555 picosecond. When you look at whole
1:57:57time constraint, it is 70 picosecond.
1:58:00So, it means that there is a violation
1:58:02in here because
1:58:05I was saying that after this rising edge
1:58:07of this clock,
1:58:10it's a new data shouldn't come.
1:58:15Bet- between rising edge and after 70
1:58:18picosecond. During this interval, a new
1:58:20data shouldn't come. But it came at 55
1:58:23picoseconds. After 55 picosecond, it
1:58:26came. This is a violation. This is a uh
1:58:29this is a violation of the this for this
1:58:32flip flop. It violates the whole time
1:58:34constraint of this flip flop.
1:58:35So, in this case,
1:58:39what should I do?
1:58:40I have to do this path a little bit
1:58:42slower because this path is very fast
1:58:45and due to this is very this is fast,
1:58:48while this flip flop is sampling the old
1:58:50data, the made, data arrives
1:58:52immediately. So, I need to make this
1:58:54that a little bit slower. So, how can I
1:58:57do it? I can add a buffer in here. So,
1:58:59if I have add a buffer, for example,
1:59:01just buffer,
1:59:02I am adding another 30 picosecond, not
1:59:05not 30 picosecond, 35 picosecond because
1:59:08gate delay was 35 picosecond. I added
1:59:10another 35 picosecond. So, when I add
1:59:13another 55 + 35,
1:59:16then
1:59:17it is fine. It is the 90 picosecond, so
1:59:20it
1:59:21it complies with the hold time
1:59:22constraint.
1:59:24Uh
1:59:24Could you understand this point?
1:59:27Hold time?
1:59:31No?
1:59:36So, hold time actually is related, yeah,
1:59:39to
1:59:41this flip-flop
1:59:43while clock when clock comes,
1:59:45we said that
1:59:47data must be ready
1:59:50during this T setup time.
1:59:53And it must be stable after rising edge
1:59:57during this T hold time.
2:00:00But, what if, for example, for this
2:00:02flip-flop,
2:00:04when the clock comes, clock rises,
2:00:08while this flip-flop samples the data at
2:00:11this point,
2:00:12this flip-flop sends new data.
2:00:17In this case, this flip-flop cannot
2:00:19sample
2:00:20in a healthy way
2:00:22because it violates this whole time
2:00:25period. While we are sampling the old
2:00:27data, new data comes. And in this case,
2:00:30we don't know. We sampled maybe old data
2:00:32or new data. We don't know. This is a
2:00:34violation for this flip-flop.
2:00:37So,
2:00:38and in here, according to our
2:00:40computation, we had a hold time
2:00:42violation because this path was
2:00:44providing the data very fastly
2:00:47before this flip-flop samples to old
2:00:50data.
2:00:51So, in this case, it
2:00:54this
2:00:55circuit will not reliably
2:00:58run.
2:00:59Uh and in order to solve it,
2:01:01we told that we need to make this path
2:01:04slower.
2:01:06So, to make this path slower, we just
2:01:09added a buffer in here. So, when we add
2:01:12a buffer in here,
2:01:14we it is like adding a
2:01:17extra 35 picosecond. We are making
2:01:20this path a little bit slower, so that
2:01:22while this flip-flop samples to old
2:01:24data, new data cannot arrive.
2:01:28So, this buffer makes this path a little
2:01:29bit slower.
2:01:32And in this case, hold time constraint
2:01:34is also complied. No problem in hold
2:01:37time constraint.
2:01:39I think setup is mostly most time setup
2:01:41is clear, but hold time is people are
2:01:43more confused about it.
2:01:46Uh unfortunately, in people I think
2:01:49they should be uh
2:01:51they should be they should teach them
2:01:53during the digital logic course.
2:01:56Uh because this is very fundamental
2:01:57concept, but unfortunately, they are not
2:01:59teaching well. Uh
2:02:02But maybe if you don't understand still,
2:02:04we can do it one more time later.
2:02:07But
2:02:08I think we need to finish the class.
2:02:12And uh for the power also, I mentioned
2:02:14about the timing in here, and also
2:02:16another concept related to digital
2:02:18circuits power. Uh power is the energy
2:02:20consumed per unit time. There are two
2:02:22types of power, dynamic power and static
2:02:24power. And you can see the formulas
2:02:27uh about the power.
2:02:29Uh since we are changing the circuit one
2:02:30and zeros, of course, we are charging a
2:02:33capacitor and discharging a capacitor.
2:02:35Of course, it consumes some power.
2:02:37And these are the
2:02:39formula formulas to con- compute power.
2:02:43Uh, dynamic power is related to changing
2:02:46because we are charging and discharging
2:02:48capacitors and static power is the
2:02:50leakage power, like leakage power. If
2:02:52you apply a
2:02:53in a transistor,
2:02:55even you don't change the this input, I
2:02:59assume that this input one,
2:03:01uh, it doesn't maybe
2:03:03assume that this is a PMOS, okay? It
2:03:05doesn't conduct. Still there is a small
2:03:07leakage.
2:03:09And this small leakage causes the static
2:03:11power consumption. Even there is no
2:03:13gates are switching, it it consumes some
2:03:15power. Dynamic power is switching. For
2:03:18example, you change it, you have an
2:03:20inverter, for example, you apply 1010 in
2:03:24order, it is changing 0101. So, you are
2:03:27switching always, so it consumes power.
2:03:30This is the static power consumption.
2:03:33So, these are the concepts you need to
2:03:34know. Uh, so
2:03:37as the last slide, uh, the the course
2:03:39assumes a fair knowledge about digital
2:03:41circuits. Uh, not much timing or power.
2:03:44Uh,
2:03:45for example, if you don't know hold hold
2:03:47time, it is fine. Uh, but you need to
2:03:50know at least what these gates are and
2:03:53what is finite state machines, what
2:03:55sequential gates are, what is flip flop,
2:03:57what is latch. You need to know them.
2:04:00Uh, for timing, I know they are not
2:04:01teaching well. Uh, for this reason it is
2:04:04acceptable. Uh,
2:04:06but if you don't know,
2:04:08for example, gates or finite state
2:04:10machines, this course is not for you.
2:04:12So, you need to pay attention to this
2:04:14point.
2:04:15Uh, so if you are not much familiar
2:04:17about these concepts, uh, either you can
2:04:19refresh, for example, maybe you you have
2:04:21forgotten, no problem, you can refresh
2:04:24your knowledge.
2:04:25Uh,
2:04:27or you can work more to learn the basic
2:04:29concepts. Uh, but we are as I told you,
2:04:31we are not for we we are not going to
2:04:33focus on digital circuits, analog
2:04:35circuits, devices, or physics. I will
2:04:37not show any NMOS transistors. By using
2:04:39this fundamental knowledge, we are going
2:04:41to build more complex processors. For
2:04:43this reason, the concepts that I show
2:04:45you is very important. You need to know
2:04:47them. You have to know them in order to
2:04:48take this class.
2:04:50So,
2:04:51and this is the
2:04:53week for the add-drop, so you can review
2:04:56your your selection in the class.
2:04:59Uh so, we can flash finish the core
2:05:01class in here.
2:05:03Uh if you have a question, you can ask.
2:05:06And also, if you want to review some
2:05:09concepts
2:05:10concepts, you can write me. Maybe we can
2:05:13do an office hours, most likely online
2:05:15office hours. Uh generally, I am
2:05:17spending my
2:05:19one one day in a week in here.
2:05:21In Wednesday, I'm in here, but I don't
2:05:24have room yet. Uh you can come in
2:05:26person, or maybe you can write an email
2:05:28to me, and I can show you. And also, I
2:05:30have TAs actually in this class. Uh so,
2:05:33they can also help to you. Uh any
2:05:35questions?
2:05:36If no questions, we can we can finish
2:05:38the class.
2:05:40Okay?
2:05:42Then, see you next week, inshallah.

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