YT YouTube2Text

YouTube2Text → Transcripts → EECS 373 - Fall 2026 - Lecture 7: “Midterm 1 Review"

EECS 373 - Fall 2026 - Lecture 7: “Midterm 1 Review" — Transcript

by Interactive Sensing and Computing Lab · 13,221 words · 1,976 segments · language en · Watch on YouTube

Open in transcriber Summarize with AI Download SRT/VTT

Full transcript

0:00All
0:04right, we can get get started. Let's see
0:09and push this there. Okay,
0:14so as we discussed the exam uh sheet was
0:17uh data sheet was released on Monday. I
0:20only saw one question I haven't had a
0:22chance to respond to, but this is your
0:24chance. If you have confusions about the
0:26data sheet, you can ask. Uh solutions
0:28for homework 3 were posted last night.
0:31There was a little uh confusion about
0:34the very last section uh of the design
0:36part about what to actually put on that
0:38APB di timing diagram because the
0:41question there's multiple ways to solve
0:43part three. So as long as you put down
0:46something that was plausible, you'll get
0:48points. I don't you know I'm not going
0:49to penalize you for my error. Um, and I
0:53told I'll make sure the graders know
0:54that as well. And then uh exam will be
0:57on Friday. All this lecture is about
0:59going over the exams. Are there any
1:01questions to start with? Yes.
1:07>> Oh, yeah. Sorry. Well, yes, it's in DAO.
1:10In fact, we'll go over that in just a
1:12second, but thank you for pointing that
1:13out. Say that right now.
1:16And
1:19DAO.
1:21Nope, not Dowax.
1:24What other questions you got?
1:28All right, we'll get started. So,
1:30logistics, we'll do a course overview
1:32and if there's time, uh, we can walk
1:35through some of the design problems if
1:36you would like. All right, so Oh man,
1:39you're right. These slides did not get
1:40open, get updated. Um, but that's not
1:44the exam location. We'll talk about that
1:45in a second. So closed books, closed
1:47notes, don't bring
1:52the reference sheet. So basically the
1:54packet that you have now, you'll get a
1:55fresh copy of it for the exam. Uh you
1:58can bring like a four function
1:59calculator, scientific calculator. Uh
2:01don't bring like a TI89, you know, you
2:04can just put any amount of information
2:05on that. So just bring a normal
2:07calculator if you would like. There's
2:09not a lot that we need calculations for.
2:11And if you felt like, oh my gosh, like I
2:13don't have a calculator and I need to do
2:15some math. You could just write on this
2:17exam. This is the calculation I want to
2:19do. The answer would be at this right.
2:21I'll figure it out. So I'm not going to
2:24it's not like trying to nitpick like did
2:25you get every single thing exactly
2:27correct. A lot of strategy exam is just
2:29saying this is what I intend this is
2:31what I think and then making the
2:32attempt. So we'll get to that, but give
2:34us as many opportunities to give you
2:37points as possible.
2:39Uh yeah, phones must stay in your
2:40pockets and we'll make a timer or a
2:42clock available
2:44and uh we'll figure out how to do that.
2:47Okay, [snorts] we actually have three
2:49rooms. Uh kind of painful. Uh
2:52approximately these are your uh it's
2:54just by make it easy. I just assign
2:56people. I don't really care where you
2:58go. Just can't all be in one room. And
2:59so you can look on the class assignment
3:02page all the way at the bottom and you
3:03can find your name and that's the room
3:05you've been assigned to.
3:08just alphabetical and it's they're not
3:10all the rooms are the same size. So,
3:11we're trying to do some load balancing.
3:14Any questions on that logistics?
3:23Okay.
3:25All right. So, your goal is you are here
3:28to maximize points. That's all you're
3:30trying to do. You don't even have to
3:31know embedded systems. You just get
3:33points on exam. I understand the game.
3:35It's totally fine. Let me tell you how
3:36to do that. So don't spend too much time
3:38on any one problem. Of course, leave
3:41yourself for design problems. Uh time
3:43for the design problem. State your
3:45assumptions. If we made some weird
3:48thing, it's like ah it was ambiguous. Is
3:51this bit supposed to be high or low? And
3:53we just didn't say. I don't know. We're
3:54insane people. Just say I assume this.
3:56If it's a reasonable assumption like you
3:58didn't have that information, we'll take
4:00it. If it was like I assume register uh
4:03the GPL register is malfunctioning.
4:05Yeah, that doesn't we're not going to
4:07that's not a valid assumption. But you
4:09know there are some times when there's
4:10ambiguity just say what you assume. Uh
4:13show your work explain what you've done.
4:15Uh you get lots of partial credit
4:17especially on the on the uh design
4:19problem. Um but without showing anything
4:22else without giving us any information.
4:23It's rare right? So give us all the
4:25reasons to give you partial credit. A
4:27sentence that says this is what I think
4:28the the APB should do for instance.
4:31Great.
4:33Um, yeah, data sheets. Uh, [snorts] we
4:35talked about this before, but you know,
4:37go on look over the data sheet
4:39beforehand. You should be able to figure
4:42out what the design problem is by
4:44reading the data sheet.
4:47Does anybody think that's true? Has
4:48anybody read the data sheet? Do you
4:50think you can uh figure out what the
4:52design problem is?
4:54Not we're not trying to hide it from
4:56you. we're there's going to be certain
4:58things that you have to figure out, but
5:00you know, it's not we're not trying to
5:01make it a mystery. It's also once you've
5:03done embedded assistance enough times,
5:05like you're like, "Oh, yeah, this really
5:07is these little connecting pieces, which
5:08is the problem, not the actual modules
5:10themselves."
5:12And so, a lot of what you're going to do
5:13on the exam is just um do the connecting
5:16pieces. Uh and if we find any major
5:19errors or issues with the data sheet,
5:21we'll update them. Well, um, it's a live
5:23document, but we'll update it on Slack
5:25so you know, so you're not caught off
5:26guard. Um, yeah.
5:30Okay. So, what to study? Homeworks,
5:32labs, [clears throat]
5:33old midterms are on the website.
5:36Uh, you know, the homeworks and the
5:38midterm, the midterms can be like the
5:40homeworks and the past midterms. There's
5:41no real surprises. Um, yeah. So, any
5:46questions so far?
5:49All right. Any questions about the data
5:51sheet?
5:54Do you want me to go over it?
5:57Yes. You say I see see people say yes.
5:58Please do that. Okay. Let's see.
6:04Some people lots of people maybe I
6:06misunderstood something. A lot of people
6:07are asking for access to this particular
6:10the sheet that caused that that is
6:12embedded here. I don't think you need
6:13access to the sheet. So if I declined
6:14you and you felt like I shouldn't have
6:16uh your request, just go on the website.
6:18It's right there.
6:20Um,
6:22all right. So, you have your fictional,
6:24you know, uh, M, uh, Cortex M4
6:27microcontroller. It's just supposed to
6:29be the exact same thing you've been
6:31using in the lab, except we're going to
6:33remove all the superolous information.
6:35We could just give you the data sheet.
6:36It's 1,000 pages. Like, you don't want
6:39to look through that in the exam. So,
6:41we're going to make it easier for you.
6:44um you know like there's there are pin
6:48outs you can this is a same thing kind
6:50of table you'd see in any
6:51microcontroller any data sheet tells you
6:54what the pin assignments are what it
6:55does and then you have peripherals and
6:57so remember this is a contract that the
7:00software people and the hardware people
7:02are making that [clears throat] if you
7:04interact with this thing the hardware
7:06will do that task and the game of
7:08drawing peripherals is like this you
7:11have to match your contract so If your
7:13peripheral says it's uh read write, then
7:16you probably have to read write to that
7:18uh register that's in that module,
7:20right? That would be the requirement of
7:21what has to happen. Uh because when
7:23you're drawing the APB um
7:25[clears throat] or peripherals, you are
7:27the hardware engineer at that point.
7:30Um we talked about this a little bit,
7:32but there's alternate functions and
7:34you'll find that you will probably need
7:36an alternate function. And there's just
7:37a map that shows you, hey, I have to put
7:39bits in those registers to make sure
7:41that alternate function appears on that
7:43GPL pin. [sighs]
7:47[snorts]
7:48No questions about that. Everybody's
7:49like, "Yes, I believe that."
7:55[clears throat]
7:56Okay.
7:57Um,
7:59there is a peripheral on there. This
8:01magical audio peripheral. It's based on
8:03real things. Like you if you really
8:05wanted to you could go look up what is a
8:06PDM microphone and read about it. You do
8:09not need to do that. It may be helpful
8:11just if you're like totally confused but
8:13how to convert from PDM to PCM. PDM
8:17stands for pulse sensing modulation. PCM
8:19stands for
8:21something I learned as undergrad.
8:25I don't know audio on device. And so you
8:27don't know how to do how to do that
8:28conversion is you just have to know that
8:30data comes in and data comes out the
8:31other end. Yeah.
8:33question.
8:36>> All right, that's it. I'm done.
8:38[laughter]
8:42>> Um, so my question was for the alternate
8:44>> Wait, is it on?
8:49>> I'll
8:51be
8:53>> No, you guys are all
8:57>> Can you Oh, okay.
8:59[laughter]
8:59Okay. Wait for the alternate function
9:01register. Do we assume that it's GPIO
9:05like defaulted or do we have to like set
9:08it to the GPIO? Like there was like a
9:10column like that says like all of them
9:12as GPIOs. Like do we assume that it's
9:14defaulted?
9:15>> Now what
9:18does reset value mean?
9:21>> Oh,
9:22>> so your manufacturers don't just let
9:24your microcontrollers come up with any
9:26bit state. I mean, it could happen like
9:28there's thermals and there's like
9:30variations in process design. So,
9:32they'll come up in some unknown state,
9:34but you certainly don't want your
9:35microcontroller to turn on and then
9:37start doing weird things. So, part of
9:39the power on reset cycle is that they're
9:42all set to some known value. And so,
9:45here we're [clears throat] telling you
9:47that on reset, and when I mean reset,
9:49that's also power on reset. The default
9:51value is 0000 for this register.
9:56[clears throat]
9:59Who else has
10:04>> all these values like SPAC, SEO, do we
10:07need to know those or are they like
10:08reference?
10:12You only need to know
10:14uh yes we gave you some obiscation
10:17information here but uh you knowcl is a
10:20protocol for um
10:23SBI and or no it's for I squared C a
10:26protocol that you will hear about later
10:28on
10:30you don't have to worry about that
10:31that's not referenced anywhere else in
10:32the data sheet you have
10:39Okay,
10:41[snorts]
10:42you got a PCM to PCVM converter. So this
10:45is the the peripheral just like a GPO
10:48peripheral. It has some functionality.
10:50It has some registers associated with
10:51it. You know, we're telling you what
10:53these bits do. We're telling you the
10:55reset values. And so here this is laying
10:58out what the programming interface this
11:00is. The programmer should expect the
11:02peripheral to act this way.
11:06Uh there's an external microphone.
11:09Not nothing you really have to know
11:10about this. This exists. It's going to
11:12have a task. So when you're asked, hey,
11:14this thing is in your embedded system.
11:16You should at least know conceptually
11:17what it is. But again, you do not not
11:19have to know what PDM data format is or
11:22PCM data format inherently. Maybe PCM is
11:25good just to understand.
11:28Um
11:29there's a you know a screen that has a
11:32parallel interface. It talks about how
11:34this parallel interface is the pin out.
11:37Talks about how to interact with the
11:39parallel interface, what pins have to go
11:42high, what pins have to go low.
11:45And then you have the rest of the um the
11:48data sheet which is us the appendix,
11:50right? which is this is all just to tell
11:52you remind you hey if you want to
11:55remember the kind of conventions that we
11:57developed this you can do this and then
11:59uh you can look through here if you find
12:00a weird instruction that you want to see
12:02uh how it operates
12:05all right
12:07yeah
12:11the address for the data register
12:13threshold register why
12:18>> the data register in
12:20status here.
12:22>> Let me see. So,
12:25which you're talking about? Oh, here.
12:28>> Yeah,
12:28>> this is 4,000 and this is 48.
12:31>> Uh, I mean, wait, I don't
12:36like it seems like they're like I don't
12:37know far apart if that makes sense.
12:41>> They are. Oh, cuz this is a one.
12:43>> Yeah.
12:45>> Okay, here we go. I have edit access.
12:48Here we go.
12:51Let make sure this doesn't collide with
12:52other things. This is Yeah.
12:57Uh oh. Yeah, those should be
13:01should be this. I think I was just off
13:03by one. There's one. That's a th00and
13:071,000 there, 104
13:10[clears throat] and 108. Okay, that
13:12feels good. And then these are
13:16okay.
13:18I'll double check all these registers,
13:20but they seem to be about right. So, the
13:23two peripherals are off by about a
13:24thousand.
13:26>> Okay.
13:30These are normal questions. Yeah.
13:32>> Going back to the alternate function.
13:34>> Yeah.
13:34>> Does the GPI
13:37have to be configured to the alternate
13:39function and the alternate function
13:41register be configured for the
13:44>> Y.
13:45>> Okay. Just like your data sheet, just
13:46like your vice using lab.
13:49>> So then if we have a GPIO as alternate
13:53function, but the alternate function is
13:55just GPIO
13:58GPI. We're trying to make it a little
13:59bit simple for you. We could have made
14:00it way more complicated.
14:03>> GPIO meaning.
14:08>> Well, you have registers that say the
14:10mode of your GP, right? All right. So if
14:13you're in DPM mode then um you can say
14:17is it output is it input?
14:21>> But isn't that computed in the same
14:23place as not it's doing its function?
14:28>> Uh let's see. So
14:31maybe we have an error here. No. Okay.
14:33So we have a register. So here's a mode
14:35register, right? And here my mode can be
14:38input output alternate function or
14:40interrupt. You don't have interrupts
14:42yet. And then you have a whole another
14:44register where you're defining what it's
14:45going to be. So you're saying that, hey,
14:47I made it too confusing. This shouldn't
14:48exist. This is not a valid alternate
14:51function. I like that. Okay, I'll put a
14:56note here that I have to go and modify
14:58update.
15:00All right, so that's fair. So here what
15:04we're saying is uh normally it's one of
15:07these four you use these two bits for
15:10any one uh GPIO and I can make an input
15:13output interrupt or alternate function.
15:15This should not be valid. Okay. And then
15:18I'll replace that with something and put
15:20a note on PCS.
15:22All right. See would it be so easier if
15:24you could just call Infinion and just be
15:26like what what is this thing? I don't
15:28understand. And then they just edit it
15:29live for you. That would be great. I
15:31don't have that power.
15:33>> [clears throat]
15:35>> Yeah.
15:36>> Um, so
15:39register.
15:53>> Hold on. I couldn't hear all that. So,
15:54you're saying the Oh, it's only four.
15:57Okay, fine. Okay, we got a little
15:59register check.
16:01Okay, you guys
16:04like so if I went on the exam, I
16:07wouldn't really if I make that error and
16:08you guys just faithfully put in whatever
16:10the address is, I'll be like, "Okay,
16:12fine." Like, I screwed up. But we're
16:13catching it now. Check all
16:18addresses. Okay, that's kind of spelled
16:21correctly.
16:23Okay, what else you got?
16:30See this is great. You guys are helping
16:31make the exam better. Now you could
16:34write the exam problems too. That would
16:36be nice.
16:38>> All right. If there any other if there
16:39aren't any other question of the day she
16:40we should probably move on to other
16:42parts talk about. [sighs]
16:45All right.
16:48So where where were we?
16:50All right. So what are we going to talk
16:51about? Talk to be covered on the exam.
16:53So ARM of course instruction set the ISA
16:58um you should at least know how if given
17:00part of the data sheet you should know
17:01like okay how are instructions encoded
17:05how would you use them you also have the
17:07appendix as well uh how to use
17:09[clears throat] load and stores and
17:10addressing mode we talk a lot about
17:12caller poly safe and the AI and the
17:15alternate name for the AI and stacks and
17:17pointers and link registers and all the
17:19intricacies there and then that really
17:21the new concept for the course is memory
17:22map IO
17:24I talked about having these synthetic
17:26addresses versus real addresses and that
17:28you know there's memory versus uh
17:30physical memory versus registers and
17:32then there's a lot of like the ABA or
17:35the APB light version. Uh we did talk
17:37about uh interrupts but we didn't go
17:39into deep dive into interrupts and you
17:42didn't have a lab on interrupts yet. So,
17:44I might there might be like a conceptual
17:46question about interrupts, but probably
17:47not to the depth of the uh I didn't
17:51remember looking through all the W25
17:54exam, but I think they just were ahead
17:55of us in class. That's why they asked
17:58more questions about that.
18:01All right, I'll just start going through
18:03slide review and stuff. Do you have any
18:05exam other questions?
18:09Okay, so major elements, right? You got
18:12to know we have the pro in the core
18:14right we have registers we have memory
18:18and a lot of this is these are all
18:1932-bit wide the program uh status
18:22register which has these extra bits in
18:25them right so these are your alu flags
18:27and remembering how to use those uh to
18:30do if statements and branch conditions
18:33and then to connecting all this is you
18:36have some assembly so you have [snorts]
18:39instructions that only operate on the
18:42register. So these are predominant like
18:45moves, ads, all those sort of things.
18:46And then there's a second class of two
18:48instructions and they're variations that
18:50allow you to interact with memory. So
18:52you have loads and stores and then uh
18:55and those exist in code, right? And then
18:58you have um like we talked about you
19:00have branch conditions and sub
19:02[clears throat] conditions that allow
19:03you to set these flags.
19:06Uh what else do I want to say? And then
19:10yeah
19:12and then the I don't forget if there's
19:13actually a slide on this but just
19:15remembering the intricacies of uh the
19:17fact that uh you can uh the address
19:21space is for a bite but typically we
19:24think about it as words where addresses
19:26increment by four. So just being
19:28familiar and capable of inter going in
19:30between those two kind of conceptual
19:32notations.
19:35[clears throat]
19:35>> Yeah.
19:37uh what we're having this is you haven't
19:40used like
19:42>> this is just more of a this is not
19:43supposed to be a complete code just like
19:45this is where [clears throat] things
19:45exist out of curiosity
19:49>> you if if you did this then you have to
19:51go those flags are then set somewhere
19:53else further in code or they're all zero
19:55so they're going to default to zero
19:57something's going to happen I guess for
19:58the sake of this example I can switch
20:00those
20:05right So, uh, I mean, just for clarity,
20:08the alien flags are not updated every
20:10single time. They're only updated when
20:13there's an S condition or a comparison
20:14or a test. And so, if you did this, you
20:17might be running on the old decision
20:18from a long time ago.
20:22Um, yeah, we talked about different
20:25registers. They're all 32 bits. you
20:27don't really care that much about um the
20:30control register and the fault mask and
20:33the fire mask and those other things.
20:36Some of those we'll talk about later,
20:37but the program status register you care
20:39about. We don't really care about uh the
20:42main Zach pointer and then the process
20:44pointer, it's not that big a deal for
20:45this file. You can just think about it
20:46as pointer, but uh highlighted in green
20:50there is what you mostly have to think
20:52about.
20:53All right.
20:57Oh, here we go. So, memory,
21:00uh, remember here we're in this zone of
21:05ARM has allocated 4 GB of space, but
21:09it's also I think when I try and think
21:10through this, it's really good to think
21:12about the business model of ARM. ARM is
21:14not here to tell uh the manufacturers
21:18where to put their peripherals or like
21:20what their peripheral should do or how
21:22much RAM they have. they just allocate.
21:24Here's where you could put it if you
21:25wanted to.
21:27And so in this particular case, right,
21:30you're going to see that there's lots of
21:31this is examples for the STM32 cuz it
21:34has a little bit nicer documentation,
21:36but just to show off uh that I mean that
21:38your your particular device does the
21:40same thing that there's lots of reserved
21:41spaces here. So here even though they
21:44say SRAMM goes from here to here you get
21:47see lots of little blank areas and that
21:49just means that you are not able there's
21:51nothing there to write to the address uh
21:55maybe it could exist but there's no
21:57stakeholding device there and they've
22:00just chosen that from architectural
22:01point of view we don't need to fill this
22:02in there's no value for us and so I had
22:05some people in office hours asking
22:07questions about this so one way to think
22:08about this is uh you have a development
22:10here and you the town has allocated that
22:13all these houses could live there or
22:15they've done the planning and allocated
22:17the the land lots and the builder only
22:21put in houses at certain locations. So
22:23the address is there but there's no
22:24place for the people to live and that's
22:27equivalent to um how this is the
22:30addresses are implemented or allocated
22:32but just not implemented.
22:40>> Yeah. know like split. [clears throat]
22:44>> Do you do you need to memorize where
22:46those splits occur? No. That would be
22:49horrible. Can you imagine how to know
22:50that? That's why we give you a data
22:51sheet, right? This says engineers don't
22:54memorize anything. Just all you have to
22:56know is the reason why things exist and
22:58then go look up the details later
23:00because I can't I guess I'm going to
23:01give you off because I can't remember
23:03anything. So, I'm not going to expect
23:04you guys to remember any of that.
23:06Okay. Oh, good. We did have a slide on
23:09this. So we're just talking about the
23:10memory organization. The slide obviously
23:12came earlier in the lectures as well.
23:14But just the differentiation here
23:17addresses are indexed by four or by one,
23:20right? For one bite for each uh data
23:22place, right? So here we're incrementing
23:25by one value for each address. But the
23:27way we think about that and the way most
23:29operations occur is that we're we're
23:31going to rewrite this to increment by
23:33four. So each address in current bites
23:34by four and then we have a word just
23:36because most most operations are going
23:39to occur on a 32-bit word but ARM gives
23:42you this opportunity to go through and
23:45um do bite operations or halfword 16 bit
23:49operations and there are some times when
23:51just you want to really compact as much
23:52data into the space as possible and
23:54that's a useful tool. Um, also good to
23:57be backwards compatible with some uh
23:59earlier probably tool chains and devices
24:02they built. Um, and then of course you
24:05have to know your ending and be able to
24:07reason away your way through these
24:09tools. I think your idees show them
24:12usually going down. Sometimes some IDs
24:14show them going uh increasing up. So
24:16just remember to look at the addresses
24:19here and figure out if the stack is on
24:21the top or the stack is on the bottom.
24:25Okay.
24:28And then the big conceptual thing is
24:29like this is just talking about memory
24:32[clears throat] allocation,
24:34but it has no idea here where the memory
24:36is allocated. ARM in the core's point of
24:38view is everything is memory [snorts]
24:40and we're just going to use loads and
24:41stores to talk talk to it. And that's
24:43that's about it. And now um we get to
24:47the vendor side of things.
24:50[clears throat]
24:50And the vendor is going to go and
24:52distribute that map. Right? So this is
24:54that little memory allocation symbol of
24:56a map. And now that is really allocated
24:59all throughout your chip. So some of it
25:02is going to be an SRAM, right? And SRAM
25:04is very fast. It's small. It's compact.
25:07Um but the problem is when you power off
25:08the device, it loses state. So we call
25:10it volatile being a different term than
25:13the volatile for say C instruction. And
25:17then uh flash which is underneath the
25:20word code there. Flash is a data
25:22structure or memory structure that is
25:24nonvolatile. So you can power it off and
25:26power it back on. Same data is in there,
25:28but it's much larger and slower. So now
25:31we have a trade-off. If a flash was just
25:33as fast and small as SRAM, then you
25:35wouldn't need SRAM. But it's not. It's
25:37larger um slower. And so often times
25:41what happens is that your program is in
25:44uh flash and then on boot up uh it gets
25:46pushed into SRAM so that you can have
25:48faster interactions. Um and so that's
25:51there's just this definition
25:52[clears throat] of like where where is
25:53that memory and then the other
25:55conceptual break here is that um over
25:58here in the peripherals it's not flash
26:00or SRAMM it's a different type of memory
26:03it's registers and the registers are
26:05sure state holding uh storage devices
26:08but really it has this alternate
26:10functionality in the sense that
26:12especially for a GPO pin register you
26:14can put data into the output register
26:16but then something else happens right
26:17the GPO pin goes high or you can read
26:20data out of it. And the idea here is
26:23that you as the programmer are now
26:25responsible for knowing how to interpret
26:27the outputs or what that memory does. Uh
26:30the core has no idea that sending data
26:33to a certain address creates the GPO in
26:35go high or low but you as a programmer
26:37have to reinterpret what that data would
26:39mean. And that's why we have the data
26:40sheet and I talk about the registers all
26:42the time.
26:44Any conceptual questions?
26:54Okay. Uh we did talk we went through you
26:57know lecture there's a bunch of uh quick
27:00discussions about different
27:02instructions. I don't want you guys to
27:04remember instructions like memorizing
27:06instructions is horrible. That's
27:07[snorts] why we give you the data sheet.
27:08But there's probably some in general
27:10that are going to be useful. You should
27:11probably know how to use loads and
27:13stores off in all the indexing off the
27:15top of your head. uh adds, moves,
27:18branches are probably important, but
27:20that's why there's a data sheet. Um, so
27:22again, don't don't try to memorize uh a
27:25bunch of instructions.
27:28Uh you don't even have to memorize this
27:29sheet. All you have to memorize about
27:31this is that uh many instructions have
27:33the opportunity to have a ss suffix. And
27:37the suffix says that they're going to
27:39update the um program status register
27:42flags. And so this is how you would, you
27:45know, assign or set them up. Otherwise,
27:47that's all they do. There's no
27:49difference between them. And then you'd
27:50have to look into the actual uh
27:52instruction on the ARM B7M
27:56ISA. Just figure out, okay, like how do
27:58I encode the S? Sometimes you have to
28:00encode the S because there's a field.
28:01Sometimes [snorts] it's implicit in the
28:03instruction, but uh most instructions
28:06have this option where it makes sense.
28:08And those are, you know, updated here in
28:10the ALOU uh flags here.
28:17Okay.
28:18Yep. And then once you have those set,
28:21then you get to do well, you're doing
28:23branches in general, [clears throat]
28:24right? So you have branches to a label
28:27um branches to a label and then updating
28:30a link register uh and different
28:32variations of that. It's important to
28:34remember like how labels work. Those are
28:38um when you look at your disassembled
28:40code uh or you're writing code that is
28:44going to uh point to a particular memory
28:47location. But when the assembler comes
28:49through and does its job with a link
28:50linker, it resolves where those labels
28:54point to what the actual memory [snorts]
28:55address is. That's the part of the core
28:58planning process. Okay. So once you have
29:01your labels and you have your you can
29:03add and your branches you can use your
29:05branches and put conditionals on top of
29:07them. And so here's just the um a table
29:10that shows okay you could do a b equals.
29:12So what does that end mean? That means
29:14that the z flag from your alou is one.
29:17And under that condition you would uh do
29:19the branch otherwise you wouldn't.
29:23Um and then you can just work your way
29:24through to figure out what all those
29:26logical combinations are. And again this
29:27is in the uh appendix. So you don't have
29:30to memorize this stuff, but you should
29:31probably know how to use the appendix
29:32pretty uh quickly. Yes.
29:37>> Is that sign?
29:40[clears throat]
29:44>> I think it's for a constant. There's no
29:47idea of sign, right?
29:52Oh. Oh, sorry. You mean you're creating
29:54a constant, not when you are um not when
29:57you're getting data in and out of
29:58memory. Is that right?
29:59>> Yeah.
30:00>> Uh you just have to look at the the
30:02instruction of making that thing. I
30:04think you could probably it probably
30:05might be a sign extended uh instruction
30:09for making it a negative value. I'm not
30:10sure though.
30:17Okay.
30:20Uh talked a lot about loads and stores
30:22and the different variations. So you
30:24guys got the normal load in store and
30:26then the pre-indexing. So uh where you
30:30go and you're augmenting the register or
30:34the value that's stored in the register
30:35but the uh actual value stays unchanged.
30:38And the reason they have this is uh if I
30:40had set up those tables uh on the data
30:44sheet correctly with the correct
30:45incrementing addresses the trick is that
30:48you would just store the base register
30:49address of a um of that you know that
30:54peripheral and then you would just be
30:55augmenting the offset register. So
30:57that's like kind of how the assembler,
30:59the program or the compiler works. It's
31:01really storing the base address and then
31:04um
31:05uh augmenting it. Now I don't care what
31:07you guys do on the exam. You want to do
31:08the full address is fine. You don't have
31:11to use that trick of uh offsetting to uh
31:14get into uh the actual registers off of
31:17the base register.
31:20Uh and then there's a post indexing and
31:23uh pre-index or post xinding with uh
31:26updates.
31:27All right. So just an example here. Here
31:29we're going to load the value that's
31:33stored uh so the address is stored in
31:35R1. We're going to put that value or
31:37sorry the address is stored in R0 and
31:39we're going to put that value in R1. And
31:42so here again we just look here to
31:45figure out what world are we in, right?
31:46Did I did I make something crazy where x
31:50hex here and I only put the two digits
31:52instead of all digits? Well, you can go
31:54look uh here to see what the increment
31:57of memory is. So, this is actually bite
31:59uh memory layout. And now I'm going to
32:01take those four values because it's a
32:03load and not a load [snorts] bite. And
32:05I'm going to place that in the
32:06destination of R1.
32:09Uh offset addressing is where you on the
32:13fly as the um uh load is occurring for
32:19or whatever this value is is added to it
32:21and then that is placed into R1. So
32:23there's not this extra calculation that
32:25has to happen. It's not the ALOU is
32:27actually taking another cycle to add
32:29that value in there. It happens in one
32:31cycle. Although I will say that the load
32:34obviously can take multiple cycles,
32:36especially if you're going all the way
32:37out to a peripheral which is on a
32:39different clock domain, but there's no
32:41inherent penalty for doing this uh uh
32:44offset in addressing.
32:46Okay, so anyways, you've added four, you
32:48can put that back into R1.
32:51uh pre-indexing uh addressing is where
32:55here you increment this by four and then
32:58you place that value in here and here
33:00that increment has stayed there the
33:03entire time and so this is good if
33:05you're trying to like iterate through a
33:06loop or something [clears throat] that
33:07is a good way to keep track of things
33:10and then post indexing here you've
33:12offset you you uh before you do the
33:15offset you're going to take this value
33:16you're going to store into R1 and then
33:18in post you go and add four to Any
33:24questions?
33:28[snorts]
33:30Okay.
33:32Uh so we'll talk a little bit about AI
33:34stuff. Uh so the basic rules here uh
33:39yeah so R4 through R11 uh must be uh
33:44preserved. uh R12 is I threw I say be
33:48careful with it is it's the inner
33:49procedural uh register uh so it can be
33:53used in in function calls I just be
33:55careful about it when you're writing
33:56handcrafted assembly on on a real device
33:59but this is available for
34:01interprocedural calls as well as as
34:03scratch space uh R0 through R3 have to
34:06be [laughter] uh preserved um or no the
34:10the function that's or the main that's
34:12calling the function can't assume that
34:14anything's happening happening in there.
34:15Uh that's scratch space for a function
34:18uh to use. And conversely, function
34:21cannot use R 4 uh through R11. It can't
34:26uh I mean it can use them. It has to put
34:27that value to the stack and pull it
34:29back, but it has to preserve those.
34:32Maybe this a little outdated. Number
34:33three is values can be passed through R0
34:37and R1, but they can also be passed
34:39through R 0 through R3. It's just that
34:42uh ARM has this idea that that is a
34:44vectorzed
34:45uh variable for all of R0 through R3 are
34:50uh a block a unit that passes uh data
34:53back. Conceptually, you can use all four
34:56of those registers to send variables
34:58back if you want. Yeah.
35:00>> The register SP again.
35:02>> SP sack pointer.
35:04>> You can't mess that up.
35:06>> So I have to push it at the beginning.
35:10>> No, no, no. uh and maybe there's a you
35:13can't go and the sub routine should not
35:16go and overtly modify the sack stack uh
35:20pointer right so if the subruine goes
35:23and uses the sack pointer it can't then
35:26use like a load or a load value to get
35:29the data back off that it has to use
35:31sack pointer again so sack pointer
35:32should be returned to where it was
35:34before the sub routine ended [snorts]
35:39up Yeah. So, you shouldn't pop a bunch
35:42of stuff and never uh or push a bunch of
35:44stuff and not pop it, right? Cuz then
35:46the stack pointer is not left where it
35:48should be.
35:53Okay,
35:55let's see. This is kind of repeat of
35:58that. Um there is special functions
36:01where R9 can be used for other
36:04functionalities in thread mode uh as a
36:07static base register. We don't really
36:08cover them in this class in for 373. You
36:11can just assume it's a general uh
36:13variable register
36:16and R12 [clears throat] again is the uh
36:18sub routine or interprocedural uh stack
36:20scratch space
36:24any questions? Okay.
36:27Uh so let's go through a sub routine
36:29call. So here the the trick often times
36:33is that when a subruine calls a subruine
36:36so when [clears throat] you just do a
36:36normal sub routine call the link
36:38registers there it's helping you right
36:39it's your way back but the trick is when
36:41a function calls a function you need to
36:43keep track of your path back to main and
36:46so now the quad was going to have to go
36:49and pop uh and push and pop the link
36:52register so it's available uh that
36:54information is not lost so that's a the
36:56trick of doing uh nested functions
37:04Um yeah,
37:07one thing that often gets students
37:08tripped up is that uh you know the the
37:13uh when you use push or pop the order
37:16actually gets reordered. And why does
37:18that happen? Well, the order is you have
37:20to think about how is that instruction
37:22encoded, right? It's not in it's not
37:24that there is actually the compiler goes
37:27and takes that and puts it into three
37:28different pushes. It's actually that
37:30instruction can take um you know depends
37:33on the actual encoding but could take
37:35say up to eight variables. Um and so if
37:38you're going to do that like um the
37:40instruction doesn't know when it's
37:42encoded and put into binary doesn't know
37:44what order those things you as a
37:46programmer put in. Instead, it's just
37:48rule. It says this register should be
37:50done. That register should not be done.
37:53And then it just goes through them
37:54sequentially. So that's why push gets
37:57reordered. And that is different than if
37:59you made three separate push
38:01instructions then uh then that
38:04[cough and clears throat] exact order.
38:05It's just if you did three separate push
38:07instructions and then did a pop with
38:09three variables in it. Uh those would
38:11have to be in order otherwise it won't
38:13pop in correct order.
38:15So only only for the registers in one in
38:19[clears throat] one push instance or one
38:22push instruction are they reordered but
38:24not for individual push instructions.
38:26They're not reordered. The compiler
38:28doesn't know about that.
38:32>> Yes. Um, so if there's like a push
38:36instruction and then another instruction
38:38and then another push instruction, are
38:40the two registered push instructions
38:43like in order?
38:44>> No. Okay.
38:45>> Any individual instruction like these
38:47are not in order, right? You can do
38:49individual instructions could push
38:51things to the stack out of order.
38:55>> No, no. I mean like um if there's like
38:58um push like instructions, they're like
39:00separated, right? like would all
39:03register into push to be automatically
39:06sorted.
39:07>> Yeah, I mean everything everything you
39:09push will go to the stack. It's just
39:11that orders uh is reordered if the
39:16registers are put into one push
39:18instruction. But if they're individual
39:19instructions and they're done at
39:20individual times.
39:25>> Yeah.
39:27>> Should you push it out of order? Should
39:29he push out of order? I don't care what
39:30you do. I mean, what's the
39:34care?
39:36You just got to make sense, right? If
39:37you go and push them out of order and
39:39then you bring them back in in a
39:41different order and that didn't work,
39:44>> then you lose points. I don't know. But
39:46it's not like I don't it's not a
39:48stylistic choice. It's whatever kind of
39:50works.
39:52>> PC.
39:57You can do it either way. It doesn't
39:58really matter. I I don't care if the if
40:01the thing works logically, that's fine.
40:04We rarely take off points. Like I know
40:07in like some of your programming
40:08classes, they're like, "You add one
40:10extra instruction and now you're a bad
40:12student. We're going to take points
40:12off." I don't care that much. If it's
40:14insane logic, then I'm like, "I don't
40:16know what you're doing." Right? But
40:17like, did you optimize every possible
40:19instruction? I That's why we have some
40:21highlights. What is it that sometimes
40:25like if you push the like register and
40:29then you pop the PC? It's just stylistic
40:33choice. You could do it point by point.
40:36You could um you could uh because
40:39essentially the link register is going
40:40to go into the PC anyways, right? So you
40:43could just go so instead of uh you could
40:46say take the P the link register put it
40:48back in link register off the stack and
40:50then branch link register right that
40:52would be the same thing if you just took
40:53two instructions.
40:56uh we are rarely counting instructions
40:59unless it unless it says the prompt is
41:01like in the most efficient way possible
41:03or within these number of instructions
41:06you know this is a point
41:11okay
41:16let's see and the same is true for pop
41:19uh just some of the pain I don't have a
41:22diagram here uh it's just you have to
41:24remember that Wherever the sack pointer
41:27is pointing, that is the last relevant
41:30data. So in this particular example, I
41:31don't know what was there. I could have
41:32put some big value in there, but it
41:34doesn't really matter at least for this
41:36example. So the first thing when you go
41:39push something to the stack, it
41:40increments and it's going to put the
41:41data in the next location. So it's
41:44remembering is this is kind of like this
41:46off by one case. You just have to there
41:48you do have to remember something. Uh so
41:50now you just have to remember the stack
41:51pointer, how that works, how push and uh
41:53pop work.
41:55Okay. So, I'll work through this
41:57example. Uh let's see what are we doing.
42:00We have a uh assembly code. It's going
42:03to call uh square and then or quad. It's
42:06going to call square and we have stack
42:08pointer that points somewhere. And then
42:09we're going to walk through this code.
42:10So, this is supposed to be instruction
42:12space. Uh this is your stack pointer or
42:15this is your stack. Of course, it's all
42:16unified memory. There's no real
42:18difference. Um but we're just starting
42:20off here. And here's some registers.
42:22Okay. So, let's Where are we going to
42:24start? Okay, so we're going to start
42:25here. It's highlighted here the the uh
42:28disassembled code and uh decoded what's
42:31in memory. And so the program counter is
42:33pointing up here. We're going to move
42:35two into R1 that was just done or R R0.
42:38Then we're going to branch link
42:40register. So we're going to branch the
42:42link register for the next instruction
42:44here has been updated uh with this
42:47value. And then we're going to branch
42:50and we had to branch to uh quad which
42:54has been resolved. Uh here is where we
42:56see the label for quad and it's to this
42:59location.
43:01And uh let's see what do we do? Oh and
43:03in this instruction we're going to push
43:05the link register to the stack. So we
43:07have it. So quad has its path back to uh
43:11end here.
43:14Then in this trivial uh example, we're
43:17going to again branch update a link
43:20register to square.
43:23Uh link register gets updated. We go
43:25into square and multiply two things
43:26together. We branch out. Uh well, we're
43:30going to take so it's branch register.
43:31What are we going to put in the
43:32register? Transfer the link register.
43:35And now we're just going to copy that
43:36over. So that's BLR.
43:39And we're going to do quad again or
43:41we're going to go to the square again.
43:42do the same thing.
43:45Um, do that all over again. Branch back
43:47to the link register. And then the trick
43:49is this link register is the old link
43:52register, right? That was way back to uh
43:55quad. But if you're trying to quad wants
43:57to get back to its main, it needs the
43:59correct link register. Well, and this is
44:01the wrong one. So now it has to go back
44:03up to the stack to grab it, pushes it in
44:06there, and then branches back to the
44:08link register. So you could have done
44:10pop pc would have been the same thing.
44:11Doesn't really matter.
44:15Okay. What questions do you have?
44:20Okay.
44:23Okay. Memory map.io.
44:26So almost all this class is just like
44:30this and most of what we've already
44:32reviewed is, you know, extension or
44:35refinement of 373. And now we're getting
44:38to the point of like what's beyond 373?
44:41Well, that is this whole bus structure
44:42and how we interact on this little
44:45device with the external world. So,
44:47we're setting you up for that by
44:48learning how the bus system works and
44:51how buses in general work, how data is
44:54pushed around and what the goal and role
44:56of the peripherals are. We'll set you up
44:59for uh the next part of the class after
45:02exam basically what's interrupts and
45:04then how do we use all these
45:06peripherals, right? Like what are the
45:07core peripherals that are common to all
45:09embedded systems? Uh and by that point
45:11you should know like how to pass data
45:14through these bus structures. Um
45:18right so here this is just your loads or
45:20stores are going to go into your GPO.
45:22How is GPO organized? Uh there are
45:26multiple registries of course but uh for
45:29any one uh GPO slice which is actually a
45:32nice term that Infinine uses. You have a
45:36register that would represent the input
45:38register that [snorts and clears throat]
45:39represents the output and then a control
45:41register. Now of course you have six or
45:43seven other registers as well but just
45:46conceptually what do you need to think
45:47about? There is some input, some output
45:49and then some methodology for switching
45:51between them or changing your
45:52functionality that is on a slice and
45:55then you have this GPO pin here and
45:58that's this pad uh would exist well
46:01maybe it exists here but is on your
46:03piece of silicon and that is what leads
46:05to the outside world
46:07and then we're just going to concatenate
46:09those all together such that all of
46:12these slices add up to a register and so
46:16each one of these uh you know locations
46:19here registers represent the state of uh
46:22[snorts] multiple different pins on your
46:24device. So you have inputs and outputs
46:26and control registers.
46:30Assume you guys have become experts in
46:32labs but [clears throat] there's always
46:34some conceptual difference between the
46:36buttons you press in lab and like the
46:38questions that we ask here or the way we
46:40ask you to think about it in lecture. So
46:43what questions is there any like this
46:45architecture of registers and connecting
46:48that to what's actually uh the go is
46:51there any questions?
46:52>> Yeah the GPIO mode register does it all
46:57three.
46:58>> Yeah.
47:00So here I have four and so in this case
47:02it's control. So we're just saying that
47:04there's going to be a mapping. So say
47:06the lowest bit of this thing corresponds
47:09to this slice. The next bit is P 0 uh
47:120.2 two, right? So there's some mapping
47:15between those.
47:17And so if we go to the data sheet here,
47:21right? So we have the same idea here. So
47:23this is the input register and we're
47:25saying that uh it's 15 bits, right? Um
47:29and there's individual bits. These are
47:31all writes and those correspond to these
47:33GPL pins here. So um guess I don't know
47:37if we actually made it super specific.
47:39No, no, we did represent the individual
47:42input pins. So there's a mapping. It's
47:43zero here goes to GPIO zero here. Okay.
47:48And that's convenient rather than having
47:50like one D flip-flop that I have to go
47:53write one bit into this D flip-flop. I
47:55can just take the whole thing as this
47:56idea of a port and now I can update all
47:59the pins on the port with this one
48:00memory location or one reader right. Do
48:04you have a question? But when you said
48:07all the meant like depending on the
48:11binary depending on the number right
48:15[clears throat]
48:23>> yeah yeah I mean the counter example
48:26could if there's all ones and you put
48:27zeros in there it's going to change it
48:29right so if it's the output port uh yeah
48:32I mean whatever bite you put in here
48:34will update [snorts] all of these
48:36>> [clears throat]
48:36>> Right? It could just be the same thing,
48:38but it will technically put another zero
48:40in there if there's already zero and
48:43you've updated it in a sense. Now, there
48:46is a um on your particular devices in
48:49lab, there is a register that allows you
48:51to only update specific bits.
48:55>> What's that?
48:58>> Yeah. Yeah. Yeah. I think that's what
48:59it's called.
49:02That just helps you. So there is these
49:03edge conditions where by updating you
49:06can get little glitches or little pulses
49:08on your pins. Even if you put a zero and
49:10you replace it with an R0, sometimes
49:11there's a glitch on some mic controller.
49:13So that uh register helps avoid those
49:15issues. But this is a that's a small
49:17thing in the point of this lecture or
49:19what we're trying to test for in the
49:21exam.
49:23Any other GPO related questions?
49:28Okay. Where were we? All right. All
49:30right. So, we're going to concatenate
49:32all that stuff together. And the real
49:34conceptual piece here, I wish I had
49:36better diagrams.
49:38I don't know. I've been teaching this
49:40like for a number of years on uh I hope
49:43I'm getting better at explaining how all
49:44this stuff works, right? So, the big
49:46thing is the processor has store thing.
49:49It has a store instruction and then the
49:51requester is connected to that. If the
49:53requester has a little state machine
49:55that's trying to figure out is the store
49:57function is that address something that
50:00the requester is responsible for you
50:02know and so because there's certainly
50:04going to be memory locations like SRAMM
50:06where this requesttor is not it's not
50:08part of the advanced peripheral bus he
50:10doesn't care so then it's trying to
50:12figure out okay if the store is going to
50:14one of the memory addresses I'm
50:16responsible for then it has to generate
50:18bus traffic with the correct data
50:21address clock and logic control bits to
50:23send that data out in the bus. There's
50:27not just one completer or one
50:29peripheral. There's many of them. And
50:31then they're all listening for [snorts]
50:34the right control signals to respond.
50:36And then when they respond, the task is
50:39to go and put some data into these
50:41memory locations or these registers
50:43which will then connect to the GPL pins
50:46and cause it something on the external
50:48world to happen. Do I have animations
50:50for that? There we go. So those CPO pins
50:53there just represent those here which
50:55update that and pass a pin high or low.
50:58So here you're storing this the guy's
51:00point over here. You put a one in the
51:02lowest bit. You collect the correct uh
51:05memory location and that will cause a
51:07pin to go high. And so you should more
51:08or less be able to trace that signal
51:10through the whole path and be able to
51:12figure out how is logically is P 01
51:16going high.
51:19Either
51:24you guys are doing great or you're or
51:27somebody needs to ask me a question.
51:29[snorts]
51:30I shouldn't have said it that way. I'm
51:31sure there are valid questions because I
51:33cannot be this good at teaching.
51:40Oh, way up there. Fantastic. You have to
51:42be super loud though.
51:43>> Yeah.
51:44um for right there's multiple registers
51:48going in. So there's a lot of different
51:50settings that have that different
51:54registers.
51:55>> Yep.
51:57>> So sorry. So the question is this is
51:59more of a statement that for each PPL
52:02pin there are multiple registers,
52:03multiple things to configure, right? Is
52:05that
52:07>> Yeah, absolutely. Right. Like it's
52:10painful because you're like I just want
52:11it to output a one. why can't I do that?
52:14And you're like, I had to spend 20
52:15minutes with this data sheet figuring
52:16out that I had to like set the output
52:18type for something. That that is just
52:21the reality of embedded systems. But
52:24once you get good and comfortable with
52:26data sheet, you kind of understand what
52:27it's trying to accomplish and you're
52:28like, "Oh, reading through the the data
52:30sheets and okay, I've got this control
52:32method. I have input output." You'll
52:35learn the patterns that most of the
52:36companies use. Uh you should be pretty
52:39quick at it by the end of the class.
52:43Does each like
52:47>> each port? Uh we'll say each peripheral
52:51um
52:56>> uh you have to look in your data sheet I
52:58guess. So and then and Infinia nor STM
53:04makes it explicitly clear what that
53:06[clears throat] mountain is. They just
53:08say here's a register and you put data
53:10into it, it will do a thing. But you can
53:12kind of conceptually see that they'll
53:14talk about different uh maybe not this
53:16device but for timers for instance
53:19there's different types of timers.
53:20You're like well why are they making a
53:22difference between this set and this set
53:23like oh they have slight different
53:24functions that can actually different
53:26peripherals or different modules on here
53:29with different functions. Um does that
53:31answer your question? So each peripheral
53:34will have one set of
53:37>> each. So say port zero will probably be
53:41one per
53:43uh it could be that port 0 and port one
53:45are also in the peripheral. We don't
53:47actually see the details of that but
53:49it's more likely that port one and port
53:51two are in different peripherals. And
53:53then from like an IP block, I'm thinking
53:55about like in production, you would have
53:56your RTL code that represents what's
53:58supposed to be and you're just
53:59instantiating different modules that get
54:01turned into hardware and then get sent
54:03out as it should. So we don't really
54:06know, but that's a good way to think
54:07about it.
54:11Okay.
54:13Uh let's see what else we got here.
54:17Um right. And then a lot of what we're
54:19talking about is just the interaction
54:21between the advanced peripheral uh
54:24bridge and the peripherals. We are not
54:27talking about the high performance bus
54:29or the bus matrix. We'll talk a little
54:31bit about that later but for now you can
54:33just assume that this thing is connected
54:34directly to the core. It's it'll make it
54:36uh simple simpler to understand and you
54:39you learn all the basics that you need
54:40to understand. So that's the requester
54:42and those are the completers. Uh we
54:44talked about all the ah what happened
54:46here? Okay, we talked about all the
54:48different nets that are between them. So
54:49you have P write, P address, and we
54:52simplify this just to say that P address
54:54is going to be the same as the address
54:56memory. In reality, it's not going to
54:58be, but conceptually, it makes things a
55:00lot simpler. And it's also important to
55:02think about what lines uh come out of
55:05your completer. So you have P ready.
55:07This is a control line, and then you
55:09have a data line. And each device
55:11according to the spec has its own each
55:14peripheral or completer has its own data
55:17path backwards uh to the bridge. So
55:20there's no bus negotiation. Uh the AP
55:24bridge or the requester sends the same
55:26data sends the same address to
55:29everything. Uh but then the control
55:31lines tell which completer should
55:33respond. Then when the completer is
55:35ready, it can send uh put data back out
55:38on his particular go. uh or as
55:40particular bus line. Uh here's the
55:44diagram I was expecting and here's just
55:46showing when you have multiple here you
55:48have multiple uh P data lines PR data
55:51lines and then P ready lines. So each
55:54one each peripheral or completer will
55:56have its own set of buses back. Yeah.
55:59There's no there was setting like a
56:02regular
56:09uh there's no inherent reason why it
56:11couldn't but you don't it doesn't know
56:13how long it's going to take and so how
56:15the uh spec is written it just waits the
56:19bus is not allowed to do something else.
56:21uh the high performance bus gets around
56:23that by having these uh pipeline
56:25transactions and having different
56:27channels but the peripheral bus generate
56:30it does not inspect does not allow that.
56:34[clears throat] Okay. And then we go
56:36through the the the signals again. So we
56:39have setup and access. So here we have
56:42this is the address of the peripheral
56:45and the peripheral address um yeah is is
56:49sent to everything we have a bit that
56:51defines read or write and remember I got
56:54this question a couple times there's
56:55nothing special about T0 or T1 really
56:59you could just start the whole problem
57:01could just start at T1 you don't even
57:02need this space here there's nothing
57:03special about it we're only really care
57:05about the setup phase and then the
57:07access phase setup phase is you're going
57:08to instantiate these signals The
57:11requester is going to instantiate these
57:12signals and then it's going to tell uh
57:15the completer hey those things are valid
57:18by raising P enable I
57:21[snorts] and P select is peripheral
57:24specific uh there's one P select for
57:26each peripheral I send data a data bus
57:29has to be established and then this is
57:31the P write data which is comes from the
57:34peripheral and we just here this is
57:36saying we don't know what it is or maybe
57:38it doesn't matter and here we don't know
57:39what it
57:41We're just in this nomenclature we're
57:42showing it's defined here
57:45and then when P ready is only valid when
57:49the device is enabled. So in this
57:51particular nomenclature here they're
57:52showing it does not matter what it is
57:54but it does matter here and it just
57:56happens to be that P ready the
57:58peripheral can respond immediately. So P
58:00ready is pulled high and then on the
58:02next clock cycle the uh completer knows
58:06that it can clock in the data or clock
58:08out the data whichever is the
58:09appropriate thing to do. Uh yep
58:14questions yeah
58:23>> no I don't care
58:25um
58:27like that [snorts] you're talking about
58:28this little line.
58:29>> Yeah. Yeah, it doesn't matter.
58:32That's just we're just using what the
58:34spec is. So you guys, if you read the
58:36spec, it's not completely different.
58:38[snorts]
58:41Yeah.
58:42>> Um for this example,
58:45right data. Okay.
58:49[snorts] I'm kind of confused
58:52and you have right on what is P right?
58:57[snorts]
58:58do anything at once.
59:02>> Uh so you're saying this is a write
59:04function. This right is high, right? And
59:06so the requesttor is pushing data in
59:08there.
59:09>> And you're saying like shouldn't P write
59:11data? This doesn't even part of this
59:14transaction. Why is it doing anything,
59:15right? [snorts] P read data, PR data,
59:18right? Yeah. So um it's could still be
59:21valid that that thing changes. It's just
59:24in this thing uh the requesttor will not
59:27pay attention to it
59:30like there's it's own bus so it could
59:32you can imagine that what do you you
59:34could just imagine that something is
59:36happening it's not a requirement that is
59:37data one
59:39>> so you could
59:41>> yeah you could have gr [snorts]
59:53So P enable goes high but then P ready
59:56does not go high.
59:59P Ready is going to stay low. Do I have
1:00:01a slide on that? No. Um so if P So who
1:00:07decides if there's a weight phase?
1:00:11>> Well, what does it the requester or the
1:00:13completer?
1:00:15>> It's the completer. The completer
1:00:17decides if there's a wait phase. the
1:00:19requester doesn't know if there's a
1:00:22white face. Um, so the completer how it
1:00:25indicates that I'm not ready to do the
1:00:27pass and usually it's a slash interact
1:00:29data is that it's going to hold load. So
1:00:33we can assume on an exam for instance
1:00:35[clears throat] or homework that if it's
1:00:36just a deep flip-flop that's the only
1:00:38thing you're waiting for, it's going to
1:00:39be done in one cycle. But if there's a
1:00:41special module that says, "Oh, it takes
1:00:43a bunch of time. There's some hint that
1:00:45goes high or something." Well, then
1:00:46you're going to have to say, "Well, it's
1:00:48not going to be ready immediately,
1:00:50right?" So somehow P is going to have to
1:00:52be held low until the circle is ready
1:00:55and then it'll be raised.
1:01:03Uh, okay.
1:01:05And we'll go through this example again.
1:01:06We got a couple minutes. Um
1:01:10so here this is example was we have the
1:01:12requester talking to two completers and
1:01:14then we have different address spaces
1:01:16right and then we're going to do this
1:01:18task of we have uh some variables put
1:01:22into registers uh in the core and then
1:01:25we're going to store some values. So
1:01:27what's going to happen from a the course
1:01:29perspective is that it's going to point
1:01:32to uh the value in R1 represents the
1:01:35memory address and then it's going to
1:01:37increment by four and store a value in
1:01:40there. So in this case it's coffee.
1:01:44But so that's the core's perspective.
1:01:46What's really happening is the core is
1:01:47going through all of here. And now we'll
1:01:49look at the bridge interaction here. And
1:01:51before I made it too confusing for you
1:01:53guys. I made the question and I I was,
1:01:55"Oh, look how smart professor sample is.
1:01:57It's going to be really good. It's going
1:01:58to they're all going to understand it."
1:01:59And then I didn't appreciate the fact
1:02:02that I didn't well this is supposed to
1:02:06be from the perspective of each
1:02:07individual peripheral. There are not two
1:02:09buses, right? Um so here we can let's
1:02:13redo that experiment. Okay, we'll redo
1:02:15it just just looking at just the bus
1:02:17signals, not what is input into the
1:02:20individual peripherals. Let's look at
1:02:21from just the bus signals. And so here
1:02:24we have a clock going through and
1:02:26there's an address. Well, what's the
1:02:27address? Uh, come on builds. Uh, oh no,
1:02:32you bad thing.
1:02:35That's supposed to be four cuz we're
1:02:38supposed to increment by four. Oh, bad
1:02:40professor. Okay, so this is supposed to
1:02:42be four.
1:02:44Um, and then it's a write instruction.
1:02:46So write goes high.
1:02:49And then oh [snorts] and I think the
1:02:50clock the clock cycle is right and then
1:02:52P select. So P1 is selected. So because
1:02:54we're in this address range here we're
1:02:56not in this address range and this is
1:02:58the this is what denotes right if you're
1:03:01in a valid address range which um
1:03:04peripheral gets selected and then after
1:03:08here's the setup phase after data has
1:03:10been all this data has been set up then
1:03:13uh you're going to go to enable. Oh I
1:03:15guess right should have come up here but
1:03:17then we have coffee. So this is the
1:03:18data. Now remember this is going to all
1:03:20devices and we're going to denote here
1:03:22that P select has its own path uh P
1:03:25select for peripheral one P select for
1:03:27peripheral 2. There's a different data
1:03:28path back for peripheral one and
1:03:30different peripheral 2 for P ready. And
1:03:33then P ready responds that it is ready
1:03:36to latch in that data. There's only
1:03:37registers in there and P ready P select
1:03:40is I don't it's don't care but in this
1:03:42particular case we held it low. Okay. Is
1:03:46this Yeah. No.
1:03:48>> Does the um setup please have to start
1:03:50at the beginning of the class?
1:03:53>> The beginning of a what cycle?
1:03:56>> Yeah.
1:03:59[clears throat]
1:04:00>> I don't know where else it would start.
1:04:01Yeah. I mean the whole thing is is
1:04:03written on a clock. So yes, it has to
1:04:05start at a beginning of a clock cycle.
1:04:07Doesn't matter which it was. And
1:04:08[clears throat] the requesttor can have
1:04:09take his time. It doesn't have to be at
1:04:11any particular point in time.
1:04:12>> Okay. It's like if I was drawing this
1:04:14like if I like started up in the middle
1:04:16of a clock,
1:04:18>> oh, I don't care that much. Like, okay,
1:04:20so what what has to be? So, you could
1:04:22just be like, you are a lousy um uh
1:04:25completer, right? And even though the
1:04:27spec says to go high, you're just slow.
1:04:28You got a lot of propagation delay. I
1:04:30don't care as long as from the point of
1:04:33view of this protocol that when P&
1:04:34enable goes high that all those data
1:04:37lines have been set up, right? Cuz if if
1:04:40not, then you're breaking the spec. So I
1:04:42don't care as you as a student exactly
1:04:44get it just at the beginning. It could
1:04:46be a little bit late. I'm not going to
1:04:47be that latigious.
1:04:50>> Yeah.
1:04:50>> Um it says that B1 is from like some
1:04:55address to 16 bytes,
1:05:00right?
1:05:00>> Yeah. So
1:05:03like [clears throat]
1:05:04you reason about how many there are
1:05:10>> you should not reason about how many
1:05:12there are you should accept that there
1:05:15yeah you don't have to worry about
1:05:17>> okay so if let's say
1:05:22>> I mean you could envision that there
1:05:24aren't that there right but remember us
1:05:27uh assistance people we reserve things
1:05:30We say that there's memory addresses,
1:05:32but then there may not be no memory
1:05:34addresses. So just because I gave you a
1:05:37range doesn't mean well, okay, there's
1:05:40probably four there, but you don't know
1:05:41unless you look at the data sheet.
1:05:44>> Um,
1:05:45can you explain why?
1:05:50>> The P enable goes high when you're
1:05:52transitioning when the requester wants
1:05:54to transition from the access ph or from
1:05:57the setup phase to the access phase. And
1:05:59so the all of the requesters signals
1:06:03must be instantiated and stable. Then on
1:06:06the next clock cycle enable can go high.
1:06:09Now
1:06:11I guess may have misspoken earlier. You
1:06:13go into the access phase if there are no
1:06:16weight stages available. So to go into
1:06:18access phase both P ready has to be high
1:06:20and P enable have to be high. It can
1:06:22definitely be in a case where P enable
1:06:25is high, Prem is not high and then
1:06:27you're in a weight state.
1:06:30>> Yep.
1:06:31>> So we just care about if the address
1:06:35value
1:06:38>> for this example. Yes. Well, no. Uh for
1:06:41this example, can I screw it up? I4.
1:06:44[clears throat]
1:06:44So it the goal was to uh get something
1:06:49into you know zero 1004.
1:06:53I screwed that up. But because that's in
1:06:55that range then we know that P ready
1:06:57will go high and respond right because
1:07:00this circle will respond to that.
1:07:03Yeah.
1:07:04>> So for the
1:07:07skip, why does it rise and fall in the
1:07:11window? It does. Does it just fall
1:07:15essentially? Yes. But would be valid
1:07:18because you know this is just a
1:07:19register. You don't know that.
1:07:22We'll assume it's just register. We we
1:07:24never talked about the hardware. And so
1:07:26in this particular case, P ready was it
1:07:29available immediate? So this is this
1:07:32would be a valid thing. It could also
1:07:33just be high the entire time. That would
1:07:35also be valid. And it doesn't matter
1:07:38what that signal is outside of when when
1:07:41kable is low. It does not matter what
1:07:44the signal is. It only matters when
1:07:47enable is high.
1:07:52[snorts]
1:07:57[clears throat] All right. So that's all
1:07:58the review slides I have. I mean, we can
1:08:00go a little recap, but what other
1:08:03questions do you have?
1:08:05>> Any questions?
1:08:11[snorts]
1:08:11>> Yeah.
1:08:18>> Sure. We do that. We have time for that.
1:08:20What would I want to tell you here? My
1:08:22last slide is this is what you got to
1:08:23review and
1:08:27oh, the starting off point. Yes, that's
1:08:29fine. Uh, we already established that.
1:08:31So, let's see. What do you want to look
1:08:32at? How about
1:08:35uh the ones I probably know?
1:08:39>> You want this one? Okay.
1:08:43Now, remember, I don't remember this.
1:08:47Okay. So, what's your question? Just how
1:08:49>> yeah I guess like how would you
1:08:59start?
1:09:02>> All right,
1:09:04good question. [clears throat] So uh we
1:09:07try to keep this little filler text
1:09:08brief because we know it actually takes
1:09:10time to read things. Uh but try to
1:09:13extract the actual useful information
1:09:15out of this. And here first is you got
1:09:18to figure out like you're going to be
1:09:19given some wiring diagram. What is this
1:09:22thing trying to teach you, right? What
1:09:24is it trying to do? It's trying to say I
1:09:26have this push button thing and it's
1:09:28connected at some locations and then I
1:09:31have and then you're it's trying to tell
1:09:32you hey look it's at GP0 it's at GP1.
1:09:36This is where that interface is going to
1:09:37happen and then we have some other
1:09:39connection over here. Okay. Uh then I
1:09:43don't know to furnace. Sure. Now there
1:09:45you'll see some things like crystals and
1:09:47resistors. Unless it's asking you about
1:09:49that, you don't really have to know.
1:09:52Then it says, okay, here uh you have a
1:09:55display peripheral. Now this was not
1:09:58going to be in your data sheet, right?
1:09:59This is the part that you've been asked
1:10:01to integrate into this uh diagram here.
1:10:06And so it tells you how to interface it.
1:10:08What is the logic that has to occur? And
1:10:11what are you trying to do? You want to
1:10:13give your core access to this
1:10:16functionality. That's what the key is. I
1:10:18saw a lot of people, not a lot of
1:10:20people, but some people seem to be like
1:10:22thinking like in the homework problem uh
1:10:25that like the timer was already
1:10:27connected to the core and like you
1:10:29didn't have to even connect you have to
1:10:31wire it up at all. And it's like no, no,
1:10:32no. The core cannot talk to the timer
1:10:35from the homework or to the LCD screen
1:10:37uh sequencer unless you explicitly hook
1:10:40it up to the advanced peripheral bus and
1:10:42then you can talk to it through C right
1:10:46because it will do loads and stores
1:10:48which will store data into this
1:10:50peripheral. So you are hooking this
1:10:52thing up making it available as a
1:10:55resource when you're writing your C
1:10:57function.
1:11:00Any what other questions you have or
1:11:02anybody else have questions?
1:11:08All right. [clears throat] So now you
1:11:10have some functionality. Your goal is to
1:11:11get this thing connected to your
1:11:13microcontroller so that you can use this
1:11:16resource cuz otherwise there's no this
1:11:18thing diagram gives you no other
1:11:20methodology for interacting with this
1:11:22thing. It's true. You could well I don't
1:11:25think gives you any other methodology
1:11:26but um you could try like bit bang it or
1:11:29something horrible but use use the
1:11:31sequencer it's there to help you.
1:11:33[snorts]
1:11:35Um yeah and then the data sheet tells
1:11:37you hey look you have these registers uh
1:11:43do a certain function. So let me see if
1:11:45I can pull up the data sheet.
1:11:51No, that's the solution.
1:11:56All right. So, what did we what was I my
1:11:58point? What was I going to say?
1:12:06So, do you need to write anything? Let's
1:12:08look at the data sheet for
1:12:11car. So, these are right and right,
1:12:16right? You do not have to be able to
1:12:18read anything. Why does this uh device
1:12:22not have to be connected up? Why like
1:12:24why aren't you connecting this up to P
1:12:27uh R data?
1:12:30The data sheet is telling you what the
1:12:32hardware does,
1:12:35right? This is you as the programmer
1:12:37have this option. You as a programmer
1:12:39cannot read
1:12:41uh or now yeah cannot read anything out
1:12:43of this character display out of this
1:12:45peripheral. It is not possible because
1:12:47the data sheet has not given you that
1:12:49capability. Therefore, when you go over
1:12:51here, you do not have to provide that
1:12:54capability.
1:12:55Right? The this is not in part of the
1:12:57programming interface. So, why would you
1:12:59implement hardware that's not part of
1:13:00the programming interface? If you wanted
1:13:02to, you could put it over there. Uh
1:13:07I don't suppose we would take points
1:13:08off. Maybe we would. I don't know. We
1:13:09have to think about the problem.
1:13:12>> Yeah.
1:13:14And you can have like any kind of
1:13:18>> what's that?
1:13:18>> Like you can have dispos.
1:13:20>> Oh yeah, do whatever you want.
1:13:22>> Uh sometimes if it's like blank, you can
1:13:24just write in what you want. If you want
1:13:26to make up uh registers, that is your
1:13:29prerogative. Um typically we put some
1:13:32things down to help you um for a reason.
1:13:36But if you guys want to go rogue and
1:13:38make wild circuits, you can do it. At
1:13:40some point we're just going to be like
1:13:41this is too insane and take points off.
1:13:43But as long as this is also like you can
1:13:45just write on the top of this problem,
1:13:47this is what I'm trying to accomplish,
1:13:49right? That will help out a lot if
1:13:50you're doing things that seem odd.
1:13:57I recogn
1:14:14right so like here P write data is
1:14:16already 32 right [clears throat] so okay
1:14:19we defined 32 and unless it changes we
1:14:22don't know
1:14:24[clears throat]
1:14:26Okay, how else would I what else would I
1:14:27do on this problem? All right, so then
1:14:30we figured out we we've made this
1:14:32resource now available to the core
1:14:34through the advanced peripheral bus. It
1:14:36can do these tasks.
1:14:38Then what do we ask you to do? Oh, write
1:14:40the keypad. Right. So now we're going to
1:14:42write as what are we going to do? Write
1:14:44an assembly function. Oh, they gave you
1:14:47a bunch of stuff. So now the problem is
1:14:49you have to figure out what insane
1:14:51methodology did we use when we wrote
1:14:54this uh C or assembly code. Like you
1:14:56could have chosen a different way to do
1:14:58the assembly and now you're like oh no
1:15:00it doesn't match. But you go read
1:15:02through here and kind of figure out what
1:15:04the modality is for interfacing with
1:15:07those assembly. And if we went to the
1:15:10data sheet, like you know, I think one
1:15:13of the the errors would be if you just
1:15:15saw this thing, where is it? The keypad.
1:15:18And you're like, "Oh, yeah, it's a
1:15:19keypad. Cool. No worries." But you
1:15:22didn't know how it worked and you didn't
1:15:24realize that you actually had to send uh
1:15:27a bit high to order to scan through the
1:15:30rows. Now you're in trouble on the exam.
1:15:33So if there's something you just don't
1:15:35really understand, I would just take a
1:15:37time to Google it a little bit. That's
1:15:38why we're giving you the data sheet
1:15:39beforehand so you can get your head
1:15:41around what it is. And if it seems like,
1:15:42oh my gosh, in our case, I would have to
1:15:45learn how PDM works. You're like, that
1:15:48might take me a couple hours to learn.
1:15:50You probably probably off on the wrong
1:15:51foot. That's the time to come and ask on
1:15:54is that where we really have to know.
1:15:56But in this particular case, we even put
1:15:58like a little false ad symbol here. And
1:16:00then the goal was for students can go in
1:16:01here and like play with it and be like,
1:16:03oh, okay, I can read out, you know, oh
1:16:06wait, here I push this little button.
1:16:07How does it work there? You know, the
1:16:10goal was for people to have an intuitive
1:16:11understanding of how this circuit should
1:16:13have worked. I kind of used it wrong and
1:16:16so there you go. So, understand enough
1:16:18about how to use it. Uh, whatever
1:16:20peripheral we're giving you.
1:16:24All right. And we got a couple minutes
1:16:26left. What else would I want to teach
1:16:27you? Uh, so then you go through this.
1:16:29It's a little macro.
1:16:33Been asked to make a little couple C
1:16:34functions. Typically, these are all
1:16:36about knowing what address to do and
1:16:38like how to interact from a data sheet
1:16:40point of view with that peripheral.
1:16:42[snorts]
1:16:43And then you have to group it all
1:16:44together. Oh, they made you write lots
1:16:46of C that time. Okay.
1:16:50What other questions do you have?
1:16:53This is a great time cuz right now
1:16:54you're at the end of the exam and you're
1:16:56like, "Oh my god, I need to get points.
1:16:58Need as many points as possible." So,
1:17:00what do you do? You just write down,
1:17:01"This is what I'm trying to do." And if
1:17:03we're like, "Aha, they're doing the
1:17:04right thing. They just didn't like at
1:17:05least we can give you some points. Yeah.
1:17:08[snorts]
1:17:20are we always track
1:17:23[clears throat]
1:17:24[snorts]
1:17:24>> sorry keep track of what
1:17:26>> track of states like what happened like
1:17:33>> the homework problem
1:17:42>> okay that's a good question I don't
1:17:44exactly remember that exam but I would
1:17:46say, "Make a plan here." Like, "What do
1:17:50you think you're going to have to do?"
1:17:52Right? So, you should be able to
1:17:53architect. You could guess what the code
1:17:55is by looking at the design problem.
1:17:58Just the little the little blurb here.
1:18:00You can figure out what the code is
1:18:02you're going to have to write in the
1:18:04last part. And so, you could scan, it's
1:18:06probably a good idea just to scan
1:18:07through the design question, but you
1:18:09could just push out like this is my
1:18:11strategy and write it in the note of
1:18:13like how I'm going to solve this
1:18:14problem. And that might help you reason
1:18:15through like uh you know what is it
1:18:18you're trying to oh I'm going to have to
1:18:19use this thing right use this peripheral
1:18:21I made I'm going to have uh some I don't
1:18:23know whatever this go oh because this is
1:18:24using the other peripheral right and
1:18:26like so hopefully early on you can
1:18:28reason about if you have to keep track
1:18:30of state
1:18:34all right yeah
1:18:38>> like
1:18:42you can
1:18:46No, we can provide extra scratch paper.
1:18:49Does people want extra scratch paper?
1:18:52>> Okay, we will add some extra pages to
1:18:54the D sheet cuz the scratch paper, but
1:18:57you can write all over the D sheet. We
1:18:58don't want them back. I mean, we'll take
1:18:59them back and recycle them, but um yeah,
1:19:02you guys can write down them if you
1:19:04want.
1:19:05>> All right, any last questions? One last
1:19:08question. Yes.
1:19:14No, you don't need a cheat sheet. I give
1:19:16you the data sheet as it's all the
1:19:17cheating you need.
1:19:20>> Okay. Thank you.
1:19:45Thank you very much.
1:19:51What are the like one for
1:19:55one performer?
1:19:58Okay. It's like one for like

About this transcript

This page contains the full transcript of EECS 373 - Fall 2026 - Lecture 7: “Midterm 1 Review" by Interactive Sensing and Computing Lab , generated from the public captions YouTube serves with the video. The transcript has 13,221 words across 1,976 segments, with the original timestamps preserved so you can click any line to jump to that moment in the embedded player.

What you can do with it

Use the transcript to take notes, quote the speaker, build a study guide, generate a summary with ChatGPT or Claude via the YouTube Summary tool, or export it as a timed subtitle file with YouTube to SRT. You can also re-open it in the transcriber to translate the transcript into 100+ languages.

Free YouTube transcript tool

YouTube2Text is a free YouTube transcript generator — no signup, no daily limit. Paste any YouTube link and get the full transcript instantly, with timestamps, click-to-jump, translation to 100+ languages, AI prompts for ChatGPT, Claude, and Gemini, and exports to TXT, SRT, VTT, or Markdown.