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EECS 373 - Fall 2026 - Lecture 5: “GPIO & MMIO” — Transcript

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0:21All right, we can get started. Let's
0:24see. So, no real announcements. homework
0:28was posted yesterday, two days ago and
0:30is due on Monday. And then again, we
0:32have office hours after class on
0:34Mondays. And if you need you could
0:36contact me and we can find another time
0:38or there's also open open lab hours that
0:41you go to for help. Okay, so component
0:45of the day just PCBs in general just as
0:47a concept. They sound sometimes they
0:50sound overwhelming and scary, but really
0:52they are just layers of metal that have
0:55been etched into a sandwich and they're
0:57just wires. They're just routing from
0:59one place to another. The um I know
1:03OpenAI thinks they've solved it. They do
1:06all the PCBs for you. Uh I would be
1:08surprised if it really works well, but
1:10we'll learn. It's another change to the
1:12industry. Uh PCBs have special features.
1:16We'll have a lecture on PCB design in
1:17general at the end of the semester, but
1:19there's things that are here. There are
1:21pads and that's what things get soldered
1:23onto. And then there's traces. Those are
1:24the kind of light green lines that just
1:26connect things. So again, it's just
1:28wires. And then they have some holes
1:30that allow you to go from one layer to
1:31another layer.
1:34And the other thing to kind of think
1:35about with PCBs is the entire industry
1:38has tried to standardize for maximum
1:40throughput and output, right? So like
1:43resistors and capacitors and transistors
1:46and all the IC types have very standard
1:48package sizes. So you can get a resistor
1:52in a very standard size is the number it
1:55doesn't matter but it's 0603 in any
1:57variety you possibly want. So all you
2:00have to do is kind of once you kind of
2:02learn the package sizes and they're not
2:04very complicated. You've basically
2:05mastered the entire PCB industry of
2:07components. You just have to know like
2:09there's seven or eight p uh chip sizes
2:12and uh types and then you've basically
2:14figured out how to uh select them. So
2:17it's it seems daunting and and undoable
2:19when you look at a place like Digi Key
2:21or Mouser it has millions of parts but
2:24realistically it's not that much and I
2:26think one half an hour or afternoon PCB
2:30tutorial and you could be making PCBs
2:31whenever you like.
2:33Any questions about PCBs
2:36or logistics?
2:41Okay, so today we're gonna finish up on
2:43the advanced peripheral bus.
2:46Uh there's a few more slides on that and
2:47then we're going to connect it back with
2:49the GPO peripheral. That's the most of
2:51what lecture is today. So if you
2:54remember our goal in general was how do
2:56we go from the core right which is doing
3:00uh you know uh your normal processor
3:02loads and stores and uh register
3:05manipulations those sort of things and
3:06then how do we actually get data to a
3:09peripheral or outside the chip like
3:11what's that mechanism
3:13and so let's see we talked about the
3:16advanced peripheral bus which is that I
3:18should go back here the advanced
3:19peripheral bus which is the mechanism
3:22uh that we'll use to transport data back
3:25and forth. And the goal really here is
3:27just to understand generally how it
3:29works and why it works. You're not
3:31trying to figure out the most exact
3:32timing and worry about those sort of
3:34stuff. Here it's just conceptual of how
3:36to link things together and what are the
3:37constraints that have been imposed.
3:41And so we'll do a little review.
3:44So here was a timing diagram. We've got
3:46the clock. We have a a bus. And this is
3:49going to be like a 32-bit bus in our
3:51example here of the address. We're going
3:53to say if Oh, I actually have builds for
3:55this. Let's see. All right. So, we have
3:57a setup phase first and then we have the
3:59access phase. setup phase is where the
4:02bus the A bus bridge or the requesttor
4:05sets up all the signals and make sure
4:07everything is stable and then when it
4:09goes to enable then it will be the
4:11access phase and that's the time where
4:14the peripheral will either latch in data
4:16or has the opportunity to latch in data
4:18or send data back latch out data. So we
4:22have a clock. Uh the address is the uh
4:25target the register in a peripheral.
4:29It's not the peripheral itself. The
4:30address is a physical resis or um
4:34register in a peripheral.
4:37We have the uh p which decides if
4:40basically if you're doing a load or a
4:42store. But because ARM is trying to be
4:45agnostic of any particular use case,
4:47they don't call it loads and stores.
4:48They call it this uh write and read. We
4:52have uh a select signal. So this is just
4:54one bit. And the goal of this is to tell
4:56which peripheral which may have multiple
4:58registers in it should be on and
5:00responding.
5:03And then we talked about the enable
5:04which is in this particular case is the
5:06way in which the requester is saying now
5:08it's time to enter the access phase.
5:12And then we have P data write which is
5:14where we write data into the target
5:17register in a particular peripheral. And
5:19we didn't talk about it yesterday or
5:21Monday but there's also um a bus line
5:24that's called P uh R read data which is
5:27where the uh peripheral will generate uh
5:32signal you know something that's gonna
5:34be read out of the register and we sent
5:36back to the requester.
5:38And then we have the P ready line. The P
5:40ready line is where the peripheral it's
5:41the only signal that the peripheral uh
5:44well it's not there's two signals that
5:45the peripheral sends back but this is
5:46where the peripheral says hey okay I am
5:48ready to do the action that's been
5:50requested of me there could be reasons
5:52why you had to wait and so the uh
5:55peripheral will raise this line high
5:57when it is ready to do the action the
5:59action is either going to be latch in or
6:01latch out data and a lot of times in our
6:03examples is always P ready is always
6:05high because it's guaranteed that that
6:07little hardware device can uh respond
6:11within one clock cycle, but we'll see
6:13examples where that's not necessarily
6:15the case.
6:17And then in here at T3, uh data is
6:20actually latched. Now remember the T0,
6:23T1, T2, that is just the nomenclature
6:26that the the spec uses. Um it could be
6:29at any time. It doesn't really matter.
6:31Those times are not important.
6:33What questions do you have?
6:38Yeah,
6:46>> exactly.
6:53>> Like you're saying like if you're six
6:55pixels over versus this way, like I
6:57don't care. Got to get it about right
6:59because the spec doesn't care either.
7:01This pex is saying it has to do these
7:03things if you read through it, but it's
7:05leaving the timing up to the hardware
7:06designer.
7:08>> Yeah,
7:15>> it does not matter. It it's uh it could
7:17have data on that line, right? Because
7:19there's probably some register that's
7:21connected, but it's not going to be
7:23latched out.
7:27>> Any other questions? Yeah.
7:31Sorry, say it again. where the shaded
7:32areas represent.
7:37Uh so the gray areas right that is in
7:40the the spec here that's uh transition
7:43time or unknown time right so here you
7:46see P ready going high is saying well we
7:48don't know exactly when P ready is going
7:50high and that's just a symbol for a
7:51transition from one state to another
7:52state
7:58>> yeah it could be shorter
8:00uh we're just saying yeah we're just
8:02saying it's just undefined here because
8:04the peripheral is doing something we
8:06don't know what it was. It doesn't
8:07matter what the peripheral was doing. It
8:09w it was not valid until the peripheral
8:11said P ready goes high and then the data
8:13must have been valid. But before that it
8:15did not have to be valid. So it's just
8:16unknown.
8:22Okay.
8:24Um so we just introduced a new signal P
8:26ready. So we'll see a couple examples of
8:28how that works. One thing to kind of
8:31remember from the uh diagram from last
8:34from Monday is that uh each the spec
8:38says that each P ready data path or from
8:42each peripheral has its own path back to
8:45the requester. So one way to look at
8:47that is that there is one 32-bit bus for
8:50every single peripheral back to the
8:52requester. So there's no bus contention.
8:54There's no way that you're going to say,
8:56well, I have, you know, 15 peripherals
8:58and now two of them are trying to write
9:00to the same bus. That's not um it's not
9:02allowed by the spec. So, however the
9:04hardware people do it implement, it's
9:06not it doesn't matter to us for this
9:08class and for the specs point of view,
9:10each one has a bus pass all the way back
9:11to the requester, its own independent
9:13path that it can write to.
9:19Uh, okay, we talked a little bit about
9:20notation. Uh this is mostly just so you
9:23have this in the slides, but when you're
9:25doing your homework or tests, these if
9:27you use these these standard um methods
9:30here, we'll know what you're talking
9:32about. Make life easy, right? So you can
9:34specify a logical one with a VDD symbol,
9:36a ground symbol. I encourage you not to
9:38spin those around. Uh it's a lot easier
9:41instead of doing bubble logic to
9:42indicate that you're masking out a
9:44particular address. You could just write
9:46the words ma add or mask and write the
9:47address. And then you can have a D
9:49flip-flop or you can define how many
9:51bits it could be eight bits or 32 bits
9:53or whatever number you want of your D of
9:55your registers for your D flip-flops.
9:57And then there's some bus line
9:58nomenclature.
10:01All right. So let's go through an
10:02example. Say we want to read data out of
10:05a peripheral. How would you architect a
10:07peripheral to do this task? Um and then
10:10the timing diagram here is just as a
10:12reference, right? This is this thing
10:13that we basically have to meet. So as
10:16you imagine uh this is just one bit uh
10:18but we are going to take the output. Oh
10:20I switched D and Q to be be tricky so I
10:23would confuse you. Normally D's on this
10:25side and Q's on their side but here we
10:27have the output of the DFF is going to
10:29the P write uh data path and we're going
10:32in this particular case the zeroth bit.
10:34You don't want to say you're doing all
10:3532 bits that wouldn't make sense. We're
10:37doing the zeroth bit and we have clock
10:39and then uh the data the D line is
10:42coming from the pin. And then here we
10:43have this is a pull-up resistor, right?
10:46This is the idea that it's always going
10:47to be pulled up to VDD unless you press
10:49the button and then it will be shorted
10:51to ground. So that there's always a
10:53defined state. If you just had a switch
10:55there that'll always be ground, it can
10:57never be high.
10:59Uh because it's a D flip-flop, there's
11:02no weight states. We'll talk about that
11:03in a minute. You would have the case
11:05here where um
11:07uh is always ready to respond within one
11:10clock cycle. And that's all you really
11:12need technically. I mean, you could go
11:14and say, uh, here I made the assumption
11:17there's only one register in this
11:18peripheral. So, if there's only one
11:19register, it doesn't matter, right?
11:22There's no, uh, P enable, it doesn't
11:24matter. P write doesn't matter because
11:26you can't even write into it. Uh, P
11:28select doesn't matter and P address
11:30doesn't matter because this is the only
11:32thing in this particular example it's
11:33doing. So, it's not that I'm saying, oh
11:35my gosh, you have to like this is the
11:38right way. if they were really
11:39implementing it, it would be all in uh
11:40VHDL and there might be some masking
11:43anyways. But just saying for this
11:44example to make the minimum to make that
11:46diagram work, this is the minimum that
11:48you would need.
11:53All right, so we can kind of go a little
11:55bit further. What if we want to do reads
11:56and writes to a particular uh register
11:59at a particular address? So here we have
12:04Oh, well I will go back. Does anybody
12:05have any questions here?
12:11You guys are so quiet.
12:14I must be such a great teacher. Not one
12:16question. This isn't that clear.
12:22All right. All right. Let's go. Uh, so
12:25here we're going to try and do all the
12:26reads in and all the reads out. Just a
12:28register to live somewhere. There's no
12:29extra features. Uh, so here we're going
12:31to take 32 bits into a 32-bit register.
12:34So we're going to write that all into
12:35the dath.
12:37We're going to read out all the data. We
12:39have a clock. So all the the basics are
12:41there. And then because we said it's a
12:44specific address, right? Then what has
12:46to be true? You have to be uh know if
12:48you're writing into it. It has to be
12:50know if it's enabled and it has to be
12:51selected.
12:53You also
12:55have to mask for that particular
12:57address. Say there's multiple registers
12:59in here. And so say we'll mask for that
13:02and all that will go into the enable. So
13:04only when all these states are true will
13:06this allow data to be lashed in from D
13:09into the state here. Now Q can always be
13:13sending out because there's no bus
13:14contention on this as we pointed out
13:16before. So Q can always be there. You
13:18don't need to have select or anything
13:21enabling or disabling Q. Uh it's always
13:24going to be available to be read. And
13:26then this happens in one cycle.
13:30>> Yeah.
13:34Why is P ready? Ah, because this is this
13:36this a D flip-flop. There's no We'll
13:38talk about weight states in a second,
13:39but there's no delay. There's no reason
13:42for a D flip-flop not to be ready in one
13:45cycle.
13:47And so that doesn't make any sense
13:49because I didn't tell you that the
13:50alternate example.
13:55Any other questions?
13:58>> Okay. What? No, that's good. Why do we
14:02add?
14:06>> So to enable that D flip-flop to accept
14:10data in it has to be a right. Correct?
14:13Right. Has to be one and uh P select has
14:16to be selected. So this peripheral has
14:18to be selected from this from this
14:20timing diagram. Okay. So you have to be
14:23selected and you have to be right mode
14:25and it has to be enabled. we are not
14:28allowed to clock in data until the uh
14:32requester has said okay all that data is
14:34uh stable and what else we have to do we
14:36have to make sure that we're actually uh
14:38the peripheral or the requester is
14:40talking to the right register itself so
14:42we've also masked on and so all those
14:45things have to be true for it to open
14:47its gate and latch in data. Now we could
14:51argue that a real hardware designer
14:52would do something more fancy. They have
14:54to deal with all these other timing
14:55diagrams. That's fine. And we're trying
14:57to get you to think logically about how
14:58does the bus get data in and out of this
15:01thing.
15:03>> Yeah.
15:13>> Yeah. It's
15:16when I make the diagrams, I'll try to be
15:17more more clear. What the data sheet is
15:19trying to tell you here is that it does
15:21not matter. It only matters when P ready
15:24is or P enable is high is the only time
15:27when P ready is going to be even paid
15:29attention to. So the uh peripheral could
15:34just hold that low as we'll see in a
15:35second saying it's not ready to respond.
15:37But any other time it just does not
15:39matter.
15:43You have to be so loud.
15:49>> Yeah.
15:54The the reason for that was um that it's
15:57just reading out of a switch. Like
15:58there's nothing there's no action that
16:01the bus does to change the state of that
16:04previous example. All it does is every
16:06clock cycle takes the output of or the
16:08input from the the button press and puts
16:11it on Q. That's all it does. So we could
16:14have written all that stuff. It just
16:15wouldn't have made a difference in that
16:17example.
16:19No, we well we just didn't that was not
16:21what the previous one example was. It
16:23was read only. I I could have probably
16:25should have made I should have said
16:26that. But
16:29now real in real in reality you would
16:31make a thing that could read and write,
16:33right? You're never going to make just a
16:34read thing. But for that example,
16:39>> yeah.
16:44something.
16:47>> So something external like like uh say a
16:50GPO pin or something. Um well that then
16:54you'd have to have some logic. So you'd
16:56have to have some logic here. We can
16:58just kind of go back a second.
17:03So in this particular case um we have
17:06the D path can come in through there,
17:08right? And so it's not that the external
17:12thing writes in through the bus. the
17:13external thing would have to write in
17:15from some other mechanism. And so if you
17:17want to do that, say you also wanted to
17:19be able to write into this register, uh
17:21you might need to have a MX so that you
17:23could select, okay, I'm in write mode
17:25and now I'm going to write into that D
17:26flip-flop because you don't want to have
17:28a contention with that thing being
17:30driven high and the other one driving
17:31low and there be bus contention.
17:35>> Yeah,
17:41>> correct.
17:45There's being enable. Oh, it this
17:47example is that's what the bus is doing.
17:51>> Yes,
17:51>> this is this is just a statement of the
17:53bus is doing and this is the minimum I
17:55should just update this slide. This is
17:56the minimum set of things to implement
17:58that bus feature for the task of just
18:00reading a push button.
18:07>> P enables coming in here. just ignored.
18:12I I think I've It doesn't matter how you
18:17when you're doing your problems, you can
18:18put all the you can put is minimum logic
18:20to meet the goal or you can put the full
18:23logic in. It doesn't really matter.
18:24You're not going to get penalized for
18:26extra logic unless it's like crazy.
18:32Okay,
18:36you're good questions. Let's see. See
18:38where were we going?
18:42So if we kind of do by extension here to
18:45read out of Q does not matter. Q the
18:48data in Q is always available and always
18:50ready independent of all this logic over
18:52here right it doesn't matter if you've
18:55updated this or changed like if you went
18:57to the wrong address Q is still there if
19:00this was the only thing on that bus. So
19:02that's why I just didn't write it out of
19:04convenience.
19:06Okay,
19:07so we'll go forward here. We'll talk
19:09about weight states. This is when you go
19:11for the setup phase. So the requesttor
19:13has set up the address, the P right
19:16select, has set P enable, everything is
19:18ready or P right data if it's if that's
19:20what it needs. Everything is available.
19:23However, the peripheral for some reason.
19:25Oh, and then it does enable, of course.
19:28So it's go. It says now it's peripheral.
19:29It's your turn to respond. But the
19:31peripheral up here didn't matter. Now
19:33the peripheral is holding it low. Okay.
19:36Why did the peripheral hold it low? I
19:37don't know. It's not part of this
19:38problem. For some unspecified reason,
19:40the peripheral is holding that line low.
19:47Um, and so what we call that is a weight
19:50state. Because the peripheral is holding
19:51it low, now we're just waiting for the
19:53peripheral to uh complete. And it could
19:55take n periods, any n clock cycles. We
19:58don't know what it is. This example,
20:01it's two. And then the peripheral says,
20:03"Okay, I'm ready. I've completed my
20:05task. My data is ready. Whatever I have
20:06to do is ready. And now it signals back
20:08to the requester. Okay, I'm going to
20:10raise this high and saying on the next
20:12clock cycle I will be able to do my or
20:14next rising clock edge, I will be ready
20:16to do my task whether it is read data in
20:19or write data out.
20:22And so then then you officially become
20:24in the access phase and the data is
20:27latched. What questions do we have?
20:29Yeah.
20:35Yes.
20:40So, one of the challenges uh this would
20:42be different than say the high
20:44performance bus um where you could have
20:47a device that's blocking the task
20:49blocking the bus from doing other
20:51things.
20:57Okay.
21:00And then the read is the same exact
21:02thing. Uh it's just that the the
21:05direction of P write was different and
21:06the need for P read data is different.
21:09So here the data doesn't matter. That's
21:11why it's all grayed out. it it could be
21:13there or the peripheral may be changing
21:16its data as it's doing some calculations
21:18whatever it is but now it's just saying
21:20the data is not valid until it completes
21:24uh P ready goes high and then uh data
21:28can be clocked out
21:33okay so here I I did not get the prompt
21:37I wanted here but uh I can walk you
21:39through this little example here would
21:40be a more complicated example so imagine
21:43This is probably more what you would see
21:45uh on a homework assignment or
21:46something. But so here we have our our
21:49um normal signals and then we have let's
21:52see if I see it here. There is P select
21:55for the temperature. Let's just say
21:56there's a temperature sensor. There's a
21:57P select for SPI which is a
21:59communication bus. And then there's a P
22:02write data path for temperature sensor
22:04and a PT data path for the SPI bus. And
22:07then each one of those has their own P
22:08ready lines. So we made this diagram
22:11before we showed which signals are in
22:13common and which signals are unique. And
22:15so here we've just identified the unique
22:17signal and in this little example the uh
22:21requester has come in and it's asked to
22:23write to this particular data address
22:25and it's gone through it set everything
22:26up and then it came in here and it said
22:29okay I've p enabled for the p enable
22:32field and now but the temperature the
22:35thing the temperature device which is
22:36the the one that was being selected
22:38because p select goes high has kept p
22:41low and you could imagine this is a
22:43common thing with the temperature sensor
22:45um is that it needs several cycles to
22:47converge on the answer. It can't it's
22:50unlikely that the temperature sensor is
22:51going to be able to do it immediately.
22:53So then it goes through, it says, okay,
22:54I'm converging. Uh it's arbitrary that
22:57it took four cycles to do it, but then
22:59when it has the value, it puts that
23:01value on the bus, pulls up uh P ready,
23:04and then it's able to latch out. And
23:06then they're just showing here's just
23:07another example, another transaction
23:10where it's gone and send that same data
23:12over SPI where it changed the address,
23:15set everything up, set the data up, and
23:17then uh SPI ready was high and then went
23:21back down low indicating that it's uh
23:23ready to go.
23:26Any questions about this example?
23:32Brave questions. People want to learn
23:34things.
23:39Yeah,
23:44>> it's just for the purpose of this
23:45example. So, temp temp is a temperature
23:48sensor that's a peripheral. Spy is a
23:51different peripheral, which is a
23:52communication bus. And so, now I just
23:54have two peripherals. This is how you
23:56would see them. And now the the
23:58requester is communicating with each of
24:00them. They are at different addresses.
24:01That's the part I forgot to put up
24:03there. Uh and then there's different
24:05transactions that occur because of that.
24:09>> Yeah.
24:22I think what you're saying is is spy is
24:24this just spy and then okay uh spy
24:29I shouldn't have put this on there I'm
24:31trying to advance you off to lectures
24:33like six weeks from now but uh spy is a
24:36serial protocol that's only designed to
24:38go from one chip to another chip like
24:39off device and so it has a whole bunch
24:41of different constraints spy is um a a
24:45single uh has one clock line and one
24:47data line is so it's serial instead of
24:49parallel. And in the context of how this
24:52works on your devices, you don't
24:54actually send out bits to your SPI
24:56peripheral. You would send a whole word
24:57out to the peripheral and you'd say go.
24:59And then it's a peripheral's job to say,
25:00okay, well, I'm going to clock this out
25:04to this other device. So the peripheral
25:05is doing some tasks for you. And from
25:08the bus's point of view, just send it
25:10what packet to send out.
25:13Good question. Okay. Uh if you get real
25:16excited, you can there's and you enjoy a
25:18good state diagram. This is for you. You
25:21can work your way through the logic of
25:22it or you could just say I don't want to
25:24learn this. That's fine. Whatever you
25:25want. But here is the logic of the the
25:27block diagram. Uh just there are some
25:30signals we didn't go over because it
25:32would be impossible to do them all.
25:34There's like error signals associated
25:36with it when the bus transfer gets
25:37corrupted, all those other things. Some
25:39of them are listed here. This is all you
25:40need to know. And I point that out is
25:43you can go and read if if I am super
25:46confusing, you can go and read this
25:48spec. It is actually like only 38 pages
25:51at least the last version I saw. It's
25:53not long. You could go through it all if
25:55you wanted. You don't have like you only
25:57need to probably go through like four
25:58pages to understand what it's trying to
26:00do. Um unfortunately
26:03as in almost all documentation embedded
26:05systems, it assumes you have already
26:06taken this class.
26:08That's the problem. So its value of as a
26:11teaching aid is kind of low, but because
26:12it's simple enough, you can you can walk
26:14your way through it. All right. So any
26:16questions on the advanced peripheral
26:18bus.
26:24Okay.
26:26So now we'll connect it back to GPIO and
26:29we'll kind of do a walkthrough of the
26:31GPIO for your particular device.
26:34Uh so again we're over here and the
26:36whole goal is we're trying to access
26:38data in the peripheral
26:42and just to be clear oh so we have this
26:44is our chip and just to be clear all of
26:47that exists on a piece of silicon here
26:49okay and we call these things integrated
26:52circuits IC's sometimes we call them
26:54dyes this is an example of something
26:56that's unpackaged
26:58and generally I don't know if this is
27:00exactly the bus I can only imagine it is
27:03But here we've all we've been talking
27:05about so far is how do we get data from
27:06the core all this in the background is
27:09probably SRAMM maybe some flash but how
27:11do we get data from here to this to a
27:14pin on the outside so that was our
27:15entire goal how do we transfer data
27:17there that bare die is in a package and
27:21of course this has been uh acid etched
27:24off for example but this is that same
27:27chip is in there and then there's little
27:29bond wires these are gold wires that go
27:31from uh the bond pads here through the
27:35epoxy and onto this metal pin here. And
27:38so that's called a package. And again,
27:40we're just trying to get the signal off
27:41of that. And then the world that you
27:43guys see is you have your dev kit and
27:46we've soldered a chip onto your dev kit.
27:48And then there's some trace, some PCB
27:50trace that's taking that line out to a
27:53uh
27:55whatever a pad over there and or a
27:57header pin. And that's what you're
27:59measuring with your oscilloscope or your
28:00logic analyzer. Okay.
28:05And then the term chip re refers to
28:08everything here kind of, right? So chip
28:10is just an overloaded term. A chip used
28:12to be what was cut off a wafer, but then
28:14the public got it. So then the term so
28:17now anything in the package is a chip.
28:19And some people I don't think anybody
28:21calls a PCB a chip, but uh chip is not
28:24the same as a die necessarily.
28:28All right. So what's inside your GPO
28:30port? So a conceptual level, there's a
28:33register, right? This is a register. It
28:35has inputs and outputs. Uh so this is
28:38input register. It's going to take data
28:40from the outside world and store it for
28:42the uh advanced peripheral bus to read.
28:44You have a output register. So data from
28:46the bus can be read in or placed into
28:48this thing which will go out. You have
28:50some control logic here, some pushpull
28:53pads. And then you also have a control
28:56register. So this is like the minimum
28:57that you would need for a GPO uh port.
29:01So you have registers that are going to
29:02control whether it's an input or output
29:04and you have state holding devices to
29:07either hold the state of the pin that's
29:08going out or read the state of the pin
29:10coming in.
29:14You take this uh idea here and these are
29:17just individual registers and then you
29:18just concatenate these things. So each
29:21port pin has a structure like this. And
29:23now we're just going to concatenate them
29:24together to make a port.
29:29Let's see. And so uh here we just see
29:31that. So if we take every one of the the
29:34register the the input registers and we
29:36just concatenate them together. Here we
29:38have all four of them together. And then
29:40positionally it equals each one of
29:42those. So we have pin one, pin two, pin
29:43three, pin four. And we can do the same
29:45thing with the output ports and the
29:47input ports. And then let's see. Oh,
29:50fancy. Um, then we can just take all
29:52that stuff and just turn it into memory.
29:55Now, uh, from the core's point of view,
29:57that's just a peripheral memory. That's
29:59just a memory location that you happen
30:00to be able to put stores, uh, words in
30:03and out of. And so when you do the store
30:05action, right, you're going to store
30:06data in. It goes to the requester. The
30:08requester interprets that this is a
30:10store uh, with some data that goes into
30:12some location. It turns it into these
30:14bus signals. requester captures it and
30:16says, "Oh, now it's my job to update
30:19that GPO output."
30:22And so from the uh uh core point of
30:25view, it is talking to a piece of
30:26memory, but all that happens to update
30:28one of those registers there, which
30:30causes a pin to go high or low on the
30:31output.
30:36Why don't you take like 60 seconds and
30:38try to explain it to your neighbor or
30:40ask your neighbor what doesn't make
30:41sense about this? Because this is like
30:42the crux of the first half of the class
30:44understanding that whole pipeline of how
30:46you get a store gets a pin high on the
30:49output.
31:13Happy
31:16birthday.
31:40I feel
32:05Now, what do you got?
32:11You gota be real loud
32:19>> eventually,
32:21right? So store in a sense doesn't do it
32:24um directly.
32:27Processor just does this command, right?
32:28And then that command essentially gets
32:31to the requester. The requester is
32:33essentially inside the processor in this
32:35example looking at the output signals of
32:37the ALU and then it says okay now that
32:41address it's trying to write to was in
32:43range of something I'm supposed to
32:44respond to and it's a store so it's
32:46something I'm supposed to respond to and
32:48then it transports the data. How does it
32:49do that? It sets all those lines. That's
32:51like the last diagrams we looked at. It
32:52figures out how to set those lines up.
32:54It's selecting some particular
32:56peripheral out of all the peripherals on
32:58the device. It selects a peripheral and
33:01then it writes into an address.
33:03That address just happens to be
33:05represented as a GPA output and that's a
33:09that's a register. One bit of that
33:11register is some register over here
33:12which goes to a pin. Now the core had no
33:15idea what it was doing. The core is like
33:16I'm just putting data in memory. It's
33:18you as the programmer who had to figure
33:20out that if memory if a one goes into a
33:22particular register that means something
33:24happens on the outside world. So that's
33:26your responsibility as the as the
33:28programmer to interpret that. The core
33:30doesn't inherently know that.
33:34How's that feel? Is that about right?
33:37What questions you have?
33:42>> Yeah.
33:50>> Yes.
33:52>> Because and you know where that is. If
33:54you remember there's a R made a map
33:57>> that whole memory map where it started
33:59with SRAMM and then code space and then
34:01peripherals external memory external
34:04devices like they define what addresses
34:08the peripheral bus should respond to.
34:13>> Yeah.
34:18>> Okay.
34:19>> No, that's fine.
34:21Okay. This is great because if you get
34:24this slide which we've been building up
34:26to you you've understood the the newest
34:29thing we've like the only new thing
34:30you've learned so far in the course
34:31right and this is like the core crux of
34:33how microcontrollers work from an
34:35architectural point of view. So we got a
34:36core we got a processor the it's doing
34:39moves and ads and all this sort of
34:40stuff. It has two methods to interact
34:42with things outside of the processor. It
34:44has loads and stores right? So it could
34:47load stuff into SRAM. It can read stuff
34:49out of SRAM. It can do that. Now it can
34:52also talk to peripherals and the ARM has
34:55defined a peripheral space. It says
34:56here's the address of where peripherals
34:58exist and then the manufacturer of your
35:01particular device said at these
35:02particular addresses things will happen.
35:05And so uh now you have executed some
35:08instruction. The requester has been
35:10listening to the core's actions and says
35:12okay now it's time for me to take
35:14action. is going to interpret that
35:15memory location as somewhere it's
35:17responsible for and it says okay I have
35:19to write or read or whatever and it it
35:22sets up the bus transaction remember
35:23there's many peripherals on there so
35:25it's trying to get the data to the right
35:26spot um then all the peripherals are
35:29listening well potentially listening
35:32they're looking for is uh all those
35:34signals specified for me especially the
35:37P select and then it says okay well I've
35:40got a signal and I have to route it to
35:41some uh register we'll call it GPO go
35:44out. And that register is built up of
35:47little bits, right? Like each one of
35:49those bytes or bits goes in there and
35:51one of those bits happens to go to the
35:53output register of a GPO pin and then
35:56that can process all the way through
35:58here to the to the IO pin and make it go
36:00high. And you could also do it in
36:02reverse. You could do it in read where
36:04you're can set that thing up to be a
36:06read pin and then you'd go through and
36:07do a load and you could load in data all
36:10the way from the GPO pin up into the
36:12processor.
36:20I'm I'm happy to do it again. That's
36:22what's
36:27>> ah
36:28um in this magic state machine buff
36:31bubble it says I have it'll have a table
36:33full of here's all the peripherals
36:35here's address range. So it's going to
36:37say this thing acted this thing or sorry
36:40the core wants to send data to this
36:42address range that represents a
36:44peripheral of it and then it'll raise
36:46the P select line and tell that
36:48peripheral it's your time to respond.
36:50You have to pay attention to me.
36:53Does that make sense? Okay.
36:56>> Yeah.
36:57>> So in that example the AQB is being
37:00driven by both sides, right? So like the
37:02requesttor
37:03might want to select a peripheral but
37:05that might not be ready. So it waits for
37:08the first ready line for it to push out
37:11that signal back to the
37:13>> right. So it's being driven by
37:16>> but not all signals are driven by both
37:18sides.
37:19>> Not just the P ready
37:20>> P ready and and P write data.
37:23>> So there's a path for the uh requester
37:27to send data and there's a path for the
37:29completer to send data back. Now the
37:31trick is it's an asymmetrical
37:33relationship in the sense that the
37:34requester defines when you talk when it
37:36talks. It it defines everything and the
37:38only thing that the peripheral can
37:40really say or the requester or completer
37:42can say is I'm not ready. That's about
37:44all it can do. It holds the pin down and
37:47then if it has data it will send it back
37:49or if it's supposed to latch in data
37:50it'll latch it when it's ready. But it
37:53can't say I want to talk now. It doesn't
37:55have that capability.
38:00Yeah.
38:09>> Uh the we'll go into the details of
38:11control kind of to mirror what you've
38:13done in lab. Uh in this example, control
38:15is just saying is this an input or an
38:17output device basically. But there's
38:19some you have to have some control for
38:21it to be a GPIO input or output pin.
38:28Oh yeah.
38:34Can you say it real loud?
38:43>> Okay. So, how does it know? Um, so the P
38:46ready line is there to indicate that.
38:49So, let's go back.
38:59Um so here P ready is held low right up
39:03until it says I will be ready to do my
39:05action on the next clock cycle.
39:09So that's how the requester knows is
39:11this P ready or low.
39:21>> I'm sorry. Say it again.
39:24from the request.
39:28>> So, so if the peripheral needs more
39:32time, it has a method and that method is
39:34to hold P ready low. It needs more time.
39:38Um, but if it goes high, then the spec
39:43says it has to do the action on the next
39:45clock cycle. There's no like I go high,
39:47but I actually needed more clock cycles.
39:49It just says you have to do you have to
39:51latch in or latch out your data on that
39:53next rising edge. If you went if P goes
39:56high, you have to be ready. Does that
39:58answer your question?
40:03>> I'm sorry. You got to be super loud. I'm
40:05I'm getting old.
40:08>> What?
40:16>> Yeah.
40:18either
40:19has to hold low and then when it goes
40:22high it has to do it in in one clock
40:23cycle has to do on the next clock cycle.
40:25It's just a requirement.
40:28>> So there's it can't be like a
40:29multi-stage latch thing. That's not how
40:31that works. Okay. How do we feel? What
40:34other questions you have?
40:38Okay.
40:43Where did we get off to? Okay.
40:46So I mean work through the concept of
40:50this diagram.
40:52Um
40:54I think the the key is to to know is
40:56that um when you're loading and storing
40:59into one of these GPO registers, the
41:02register the hardware of the register
41:04itself is interpreting those bits in
41:06that register to do a task. And we'll go
41:10through a bunch of different tasks that
41:11can be but in this example it's either
41:13like outputting data or configuring
41:15something.
41:17All right.
41:19So a lot of embedded systems is being
41:22able to read the data sheet.
41:25Um once you know enough background that
41:27you can interpret the cryptic messages
41:28on data sheet uh you're fine. So I'll
41:31help you in a sense of walking you
41:32through the GP reports and helping you
41:34think about what are the bits of
41:35information I need to glean from the
41:37data sheet so that you can then
41:38interpret the rest of the data sheet
41:40effectively.
41:43So if you go through uh uh part 26 of uh
41:47your enormous you know thousandpage data
41:49sheet for this chip you'll come up to
41:51the GPL port and this somewhat
41:53complicated diagram uh has all the major
41:56functions that you need to think about
41:58and then it goes through and documents
41:59what their functionality is and what uh
42:02the registers do that control it.
42:07So, one concept that they have here is
42:09this idea of a pad, a port slice, and a
42:12port. And so, a pad
42:16is that one of those little bumps over
42:18here. That's the the place where the
42:20gold bond goes in. And that actually has
42:23some logic built into it. It's not
42:25purely a passive device. It has an
42:27output stage. It has an input stage and
42:29a pull-up devices. We'll go through each
42:31one of those, but conceptually that pad
42:34exists separate from everything else.
42:37Then it has what this data sheet calls a
42:39port slice, which is just one register.
42:42So remember how I had that concatenated
42:44slide of things that all came together?
42:46This is just one of those. And then
42:48you'd have say 16 of these on top of
42:50each other to make a entire port.
42:56And so here is a little bit more an
42:58alternate representation of that same
43:00thing. We have uh you know output
43:03registers and bit select registers,
43:04input registers. The reason I pull up
43:06this diagram because it's not easy to
43:08see in your particular data sheet is
43:10that on the input side there is ESD
43:13protection. So this is electrostatic
43:15discharge protection. There are dodes
43:17built into your GPO pins. Normally you
43:20never think about that and if you shock
43:23your devices still likely to destroy
43:25them even though you have ESD
43:26protection. But one edge condition that
43:28can often occur is that if you put say
43:32you have a 3.3 volt system and you put 5
43:34volts into it, what's going to happen?
43:36You're going to put 5 volts in the IO
43:38pin and VDD uh IO is at 3.3. It's going
43:42to conduct current through the thing and
43:45blow up your device. So this is why you
43:47say, "Hey, it's just an input. I should
43:49be tolerant. Well, it's not going to be.
43:50Almost all devices have some sort of uh
43:53overvoltage and ESD protection just to
43:56be aware of. You do have to control the
43:58voltages between devices or have a
44:00voltage translator.
44:03Okay, that's a side note.
44:05Um, so I tried Oh, you guys can't see
44:08anything. But, uh, here is this the
44:10input port. I tried to highlight the
44:12part we're talking about up here as well
44:13as put it up here. This is the register
44:16that represents the data coming off of
44:18the port. And here SD uh infinion says
44:22okay a port is uh made up of 16
44:27um pins even though it has a 32-bit
44:30register and the top register here is
44:33all zeros and the R here means reserved
44:36means uh well this actually means read
44:38but there's no data in here. It doesn't
44:41do anything but you can uh read data out
44:43of these registers.
44:45A nomenclature here it says PN that's
44:48because you replace the N with your port
44:51number and then the addressing scheme
44:53here. If you are in port one then the
44:56address is this this this plus one times
44:59100. So now you can see that each one of
45:02their addresses for each port is just a
45:04uh increment of each other. And then
45:08yeah and then these are the a key for
45:10these symbols. So basically data is
45:11going to come in and it's available to
45:13be read in the lower 16 bits.
45:18Uh likewise the output port is very
45:20similar. Uh it's just a register for
45:23right now. We're not having talking
45:24about how to configure it. It's just 16
45:26bits here. You can read or write from
45:29it. And it's saying here hardware can
45:31update it. Hardware can also update.
45:33That's what the H means. uh here.
45:37And how could hardware update it? We'll
45:38talk about it a little bit later, but
45:40you could have an alternate function
45:41like an SPI pin that's going to change
45:44uh this uh these registers independent
45:47of what you're doing even though it's a
45:48right pin. So basically, if it says
45:50hardware, you cannot rely on it to store
45:52data for you because something else
45:54could update it. And it provides you the
45:56lower 16 bits here representing the
45:59output of the 16 um pins.
46:03And then uh well any questions any
46:06questions
46:08you yeah
46:10>> in the case you have to make sure that
46:15variable in your code
46:18>> correct yep
46:22and hopefully our compiler will catch
46:24that but no guarantees.
46:27All right. Um let's see. And then we got
46:30to the uh there's a special they give
46:32you a special extra port. It's a
46:33modified port where you can uh you get
46:36the lower 16 bit of this register as a
46:39you can go through and let's see you can
46:41bit you can set pins or you can reset
46:45pins. So they're giving you this
46:46convenient method. So normally what you
46:47would have to do is you have to uh go
46:49and like say you want to output
46:51something and you want to change one bit
46:53you'd have to load all of that into the
46:55core change your one bit and then write
46:58it all back. if you just uh in the nive
47:00case just put one bit in there. That
47:01means you erase everything else that's
47:03in that pin. So here they're giving you
47:05the special functionality. They're
47:07saying okay you can put bits into here
47:08and we'll only either reset or set that
47:11particular pin. So it makes it a nice uh
47:14lower number of instructions to update
47:16just one pin. And they specifically say
47:18that this is a these are not physical
47:21registers. They are just virtual
47:23registers. Um basically they're just
47:25another way to get data into the
47:26flip-flop. That's all it is. And they
47:28just have a special function that if you
47:30put a one in there, if you put a zero
47:32somewhere else, it will not change uh
47:34that the function of that pin. So, it
47:35allows you to easily update things.
47:40All right. Any other questions before we
47:41go on to the control register because
47:43that's painful.
47:46Okay. So, the control register which is
47:50essentially has controls the entire
47:52function of the device does a bunch of
47:53stuff. uh they have uh and I don't know
47:57why but they say here that the lowest
48:00[clears throat] three bits is always
48:01read you can't write to it and then it's
48:04five bits then it's zero bits and five
48:06bits so they have the structure here
48:07basically they're going to give you five
48:09bits per pin to configure this uh pin
48:12and then they need four registers in
48:14total to do that
48:16and then they say they you know if you
48:18go to the next table here you have all
48:21the pins [snorts] or all the functions
48:23available able and uh those are the five
48:26bits you can put. X means don't care.
48:28But you can do things like set this is
48:30the input. You're controlling how data
48:32gets input. You can make it just a
48:34normal input pin. You can have it be
48:37pulled up or pulled down. And you can
48:39for some reason, which I have not
48:40figured out yet, you can have it also
48:42update the output register. Don't know
48:43why we want that, but I'm sure they they
48:46figured out a good reason. And then you
48:48also have the option to invert the
48:49input. Uh you can imagine that somebody
48:52had some chip and it only came in one
48:54logic state and you everything else on
48:56that bus was inverted logic and so you
48:59could spend the time in uh your al or in
49:02your core flipping that bit each time it
49:04comes in or they're just going to
49:05provide you with a functionality just to
49:07invert that bit. Uh so here this is that
49:10path you're coming in here through the
49:12Schmidt trigger. You have the invert and
49:14then you have um basically data
49:16synchronization and then you have your
49:17port. So a Schmidt trigger is
49:20particularly important and almost all
49:21devices have it. And so that's because
49:23digital signals are not always just ones
49:25and zeros. Sometimes they're crossing uh
49:29through a variety of reasons uh not as
49:31square waves. And so if you're going to
49:33go and hit some arbitrary threshold and
49:35just make ones and zeros, it can look
49:36kind of chaotic. Uh you're getting this
49:39half. This thing didn't go all the way
49:40to the top. And so you got this like uh
49:43maybe it was never intended to be high
49:44or low. Well, this one did go all the
49:46way to the top. So the schmidt trigger
49:48is a gate type of gate that has
49:52hysteresus which basically means that uh
49:54as you transition from low to high you
49:57must go very high before it'll be
49:59transitioned. And if you're going from
50:00below or high to low, you must go very
50:02low. So there's a window here. It's not
50:04just a 50% threshold. It's a structured
50:07threshold where you have to be going in
50:09the right direction uh to actually have
50:11a count. And that has a good function of
50:14actually. So here's the guard bands. you
50:17actually have to go from like if you're
50:18going high to low, you have to go
50:19through red and then to blue, but you
50:21can't just go down to red a little bit
50:23and then red again. You actually have to
50:24make that full transition and it helps
50:26clean up your waveforms. It also helps
50:28uh with metastability and other issues.
50:31And so you might be like, well, this
50:32looks like a, you know, weird signal.
50:34Like these signals do exist. This is
50:36kind of a this is a a button being
50:38debounced. Um it has some weird things
50:41in here where it has some little runs
50:42that didn't go over 50%. It has this
50:44little one that maybe didn't go high
50:45enough. And then it has the actual
50:47button press and then it gets let go. So
50:49here you don't want to get triggered on
50:51all those. You want it to really go
50:52high. You want some higher up threshold.
50:59>> Any questions so far? Yeah.
51:11>> Um Oh, they're reusing the don't care
51:13bit later on. We're going to see that in
51:15a second. It's just for that particular
51:17function, they don't care. So they they
51:19could have defined it for you. Why they
51:21didn't define it, I don't know. Some
51:22architect had a good reason,
51:25but they do use the bit. It's not that
51:26it's never used. Um,
51:30so here we have uh pull up and pull
51:32down, which are options. So uh they
51:36actually add into each one of those uh
51:39pads resistors. And those wristers allow
51:42you to pull a signal up or pull a signal
51:44down. And what does that mean? So you
51:46can select them with these uh these
51:49codes here.
51:51And that essentially means the output
51:53pin has a resistor that's pulled up to
51:55VDD and then it goes into the input. Or
51:57you could have an option of pulling it
51:58down. Why?
52:01It's resistors are relatively cheap,
52:04right? You can resistors 603 resistors
52:07less than a penny if you buy them in
52:08volumes. Why is S uh Infinine making the
52:12decision to spend precious space inside
52:15putting resistors inside that could be
52:18you know digitally selected? What would
52:19be take 30 seconds? What would be the
52:21reason why Infinion would make this
52:23choice?
52:27Why would a manufacturer of a mic
52:30controller give an option to have
52:33resistors be connected to the input pin
52:35rather than just have the board designer
52:37put resistors on the PCB itself? If you
52:39know you need them, why are you putting
52:41them on GPO pins?
52:45All right, take 30 seconds. See what See
52:46what you guys come up with.
52:52Oh boy.
52:55Yeah.
53:05All
53:29right. What do we think? Why in the
53:31world would they put resistors in a
53:33digital device?
53:40You guys are talking to each other. You
53:42have ideas.
53:49>> Why?
53:51Oh, there you go. Okay.
53:58>> All right. So the argument it's so
54:00ubiquitous, but why not just make the
54:03PCB people do it?
54:11>> Oh, so you couldn't reconfigure it,
54:13right? So this is this allows you to
54:14configure on the fly.
54:17I don't know if I've ever actually done
54:19that, but that's true. I think what they
54:21found
54:25you sell.
54:30>> Okay. I was more thinking on the P on
54:32the PCB. So, you sell the chip to the
54:34board manufacturer or the device
54:35manufacturer. You sell it to I don't
54:36know somebody and then they make a PCB.
54:38They could just put a resistor on there.
54:40Like what's the advantage here? And so
54:41it really comes out to um actual space
54:45on PCBs is so constrained that having
54:47the physical footprint became a problem.
54:50And then it's actually relatively easy
54:52that it's not a great resistor, but it's
54:54okay to put it inside. And so now they
54:56can differentiate themselves from the
54:57marketplace and say, "Hey, I have you
55:00can have less bill of materials because
55:02you can put these resistors inside." And
55:03then everybody started doing it. So it's
55:05just more like a convenience thing. It's
55:07not like uh inherently that to make
55:10these things function you would have to
55:11have it. You could just have it on the
55:13outside.
55:15All right. Uh where was I? So pull up
55:17pull down resistors. Uh other
55:19functionality. Let's see. You have a
55:20control output. What is this one? Oh,
55:23now we can control the types of outputs
55:25you're going to have. Um let's for
55:27example here you can have a pushpull
55:29output. So this is uh it looks like an
55:31inverter. It has a little controller on
55:33it. And the idea of a pushpull output is
55:35that they're really beefy uh NMOS and
55:38POSs that can drive lots of current. And
55:40this is the thing that's going to be
55:42pushing voltage or current out on that
55:44GPO pen. And either you're going to
55:46connect one or the other. You can also
55:48disconnect both so that it's not driving
55:50the pin and then that becomes an input
55:52device. So here you connect the top of
55:55course you're you're driving current
55:56out. Oops. You're driving current out.
55:58Here you're driving you're sucking
56:00current into ground essentially.
56:02Um the concept of open drain is that you
56:05only do half of that. to disable the POS
56:08on the top and they call it open drain
56:11because here the D on that N MOS is uh
56:15open to the to the world and so now it
56:18can have the option of pulling down
56:20current or not pulling any current down
56:24and so now I can leave that pin floating
56:26and you'll find that uh when you talk
56:28about I squared C buses that this is the
56:30preferred modality of how you would
56:32interact with those devices but this
56:34just showing you that you this is a
56:36different mode of operation. When you
56:37see it, you can either be um pulling to
56:40connected to ground or disconnected from
56:42that pin altogether. Those are the two
56:44two options for open drain.
56:48Uh output pins also have um alternate
56:52functionality. And what does that mean?
56:54What does that even mean? So there's a
56:57table uh table whatever 2612 that
57:00defines all the alternate functionality
57:02that the GPL pin can do. And uh thinking
57:05about spy or communication, you don't
57:07want to have a dedicated pin just for
57:09spy. That would be kind of annoying. Uh
57:12so what you can because then you
57:13couldn't use it for anything else. So
57:14what they say is a general purpose IO
57:16pin. They can configure it to run
57:18peripheral acts like other peripherals
57:20can u send data out through that pin.
57:23And so what would that look like? So
57:26here we have the this is a GPO pin on
57:29the advanced peripheral bus. And we want
57:31to add in an alternate function. So you
57:33would go look up on the table, figure
57:34out what bit pattern to put in there,
57:35and then for instance, you could have
57:37your spy will literally connect a wire,
57:39not through the advanced peripheral bus,
57:41just directly as an alternate input. And
57:43then when you configure your spy to send
57:45out data, it will pass those bits out on
57:48the pin. So this is a way that you get
57:50to reuse that pin for multiple other
57:52functions. It's not always just a fixed
57:53function device.
57:58What questions you have? Yeah.
58:02at all.
58:07>> Yeah, it doesn't go through the bus
58:09structure. It's just it's just I mean
58:10it's all on chip. Um but it just goes
58:14straight from the UR peripheral
58:17uh and makes a line to that output pin
58:20because it would just be it would cause
58:21you this extra delay if you had to go
58:23back through the advanced peripheral
58:24bus. So it's just a direct path and
58:26you'll do that for ADCs and all these
58:28other peripherals. Sure.
58:41>> What are you thinking? What's your
58:42question?
58:43>> I just how does it work?
58:45>> Ah
58:47uh
58:49so how it works is these are just magic
58:50switches. Uh we don't some people took
58:52an analog class and you could figure out
58:54that these things could be like quasi
58:56resistors and nobody cares about that.
58:58These are not amplifiers. These are
58:59switches. Okay. And all we're saying is
59:02that in this particular case, the NOS
59:05switch is closed, which means the uh
59:08ground is connected to that pin, which
59:10any voltage that's on that pin is going
59:11to be sucked down to ground. And then
59:14the the other is true as well, right? So
59:18you can pull it up to to high here.
59:20You're going to source current out on
59:21that pin up until the pin is raised to
59:23VCC.
59:25So these are just switches. uh I think
59:28uh lecture one or two there were some
59:30false ad uh diagrams to play with. So I
59:33encourage you you can click on those
59:35false ad um URLs or copy them into your
59:38browser and then you can play with the
59:39circuits you see in slides and you can
59:41just like I think getting the intuition
59:42about how circuits work is more
59:44important than calculating them
59:45calculating for this class. So go play
59:47with them.
59:48>> Yeah.
59:57No,
59:58>> it's not preferred. There are certain
59:59peripherals when we talk about I squared
1:00:01C which is a communication style that
1:00:02that's the requirement. It has to be
1:00:04that way.
1:00:05>> But why would it why would you want the
1:00:08output to be floating?
1:00:10>> We will find out. But basically that bus
1:00:12structure uh
1:00:15uh it tries to handle a case where you
1:00:18have multiple devices on the same line
1:00:21and any one of those devices could
1:00:23interact with a bus and they want to
1:00:25guarantee there's a case where two
1:00:27things can't one can't drive high one
1:00:29can't drive low and then you would you
1:00:31know short circuit. So they're trying to
1:00:33eliminate that and then this option has
1:00:35emerged as high impedance as a way to
1:00:37get around it. But don't have to worry
1:00:38about that now. You just have to know
1:00:39that it can do it.
1:00:45Okay.
1:00:49Yeah. And uh you will find out later
1:00:51that there's lots of wires. Um it's not
1:00:54always the bus is not the only way to
1:00:56talk to different devices. They have
1:00:57dedicated functions. So here the SPI
1:01:02peripheral can talk there. The ADCs can
1:01:03talk talk to the devices. And later on
1:01:05we'll learn about interrupts. So the bus
1:01:07is not the only way. The bus is just the
1:01:10primary way for the core to to send push
1:01:12data around with data being different
1:01:14than signals.
1:01:16Okay. And the last register of note here
1:01:19is that there's a pad driver mode
1:01:20register which I suppose would be I mean
1:01:22the registers are over here but it's
1:01:24really affecting uh this output device.
1:01:26And it has weird things. It took me a
1:01:28while to kind of figure out what they
1:01:30really meant but you have options to
1:01:32drive weakly to drive strong. You can
1:01:36also drive sharp and drive medium and
1:01:39drive soft. And I can't figure out what
1:01:41the difference between uh hard and soft
1:01:44and all and weak and soft and sharp is
1:01:46but kind of took me a while to figure it
1:01:49out. And so what they're saying is this
1:01:51is the drive strength of the GP of the
1:01:54uh pushpull pair. And you can either
1:01:58have it transition from high to low very
1:02:00quickly. That would be the sharp, medium
1:02:03or soft. And then you can also configure
1:02:05it to push out more current or less
1:02:07current. And why would you want that?
1:02:09Why don't you just get normal square
1:02:10waves? Well, what you find out is that
1:02:12the loading conditions of your bus of
1:02:15the off device bus like as the GPO pin
1:02:19is trying to talk to something else will
1:02:20affect your signal. And so if there's
1:02:23lots of capacitance or lots of
1:02:25inductance on that, you will get
1:02:26overshooting. So you might want to go as
1:02:28fast as possible, but then you get this
1:02:30ringing. So if you saw that you're like
1:02:32oh I am driving too strong I need to
1:02:35reduce I need to go from sharp to medium
1:02:38to soft so that I don't get that
1:02:40overshooting and that overshooting will
1:02:41cause noise and could cause data
1:02:43corruption. Um and also the drive
1:02:46strength allows you to drive slightly
1:02:48bigger things. It's not a lot more
1:02:49currents like half a milliamp versus 2
1:02:51milliamps but maybe enough to change how
1:02:53you would uh light up an LED for
1:02:55instance.
1:02:58Okay, any questions on the peripheral
1:03:00itself? And I think the real goal is
1:03:03trying to connect like, okay, I have
1:03:06some functionality here. I have some
1:03:08registers. I know where the address is.
1:03:10I can read through the data sheet and
1:03:12say, okay, I need to drive this thing
1:03:14stronger or faster. And now I can figure
1:03:16out the bit fields I would need to do to
1:03:18put into that register to control the
1:03:20function of the GPO port.
1:03:24What questions do you have before we
1:03:25move forward?
1:03:28Did you guys cover all this in lab? Is
1:03:29this a 100% review?
1:03:33Kind of like I I just pushed the buttons
1:03:36in lab. I have no idea what I did.
1:03:39Totally fine. Totally fine. I remember
1:03:40taking this class. Okay. So, what we're
1:03:43going to do next is we're just going to
1:03:45try to do an example working together to
1:03:48try to connect up a uh GPO port
1:03:55to an APB just to think through the
1:03:58logic signals
1:04:00here. Can you pass those down there?
1:04:04And there will be lots of prompting. And
1:04:06so, can you pass these up?
1:04:09And you can pass those up and over.
1:04:13And
1:04:16you can go up and over
1:04:18or over and up. There you go. Cute.
1:04:26Here. You guys might run out. You guys
1:04:28can start here. Send him that way.
1:04:41All right.
1:04:43So, we'll need lots of prompting for
1:04:45this one. So, my goal, and you're not
1:04:47supposed to be perfect at it. You're
1:04:49just supposed to think through it, is to
1:04:50give this given this data sheet, which
1:04:52I'll leave up here. So, this data sheet
1:04:54is kind of like a simplified version.
1:04:56The other one, it says it has an output
1:04:58input register, an output register, and
1:05:00a mode register. And then it tells you
1:05:03what is the functionality of those pins
1:05:05of the the the register should do.
1:05:07Right? So here it says uh you can make a
1:05:10general purpose output. You can make a
1:05:12general purpose input. You uh how many
1:05:16bits there are in the system, how many
1:05:17pads there are in the system. Okay. And
1:05:20you're also given, you know, a standard
1:05:22notation. You could use other logic
1:05:24elements if you really wanted to, but
1:05:25this is kind of standard set of
1:05:27elements. And now the goal is wire this
1:05:30thing up. Okay, so here you got your AP
1:05:34signals. And what you want to be able to
1:05:35do is uh implement a full ports worth of
1:05:38logic. So you want to be able to write
1:05:40and read and control the output
1:05:42registers and think through all the
1:05:44signals that would have to be to be put
1:05:46in here. And you should do this part for
1:05:49the full port, but you only have to wire
1:05:50up one of the pads here. And so you have
1:05:53to figure out how many bits you want in
1:05:54your registers and how they should all
1:05:56be connected. So you should be able to
1:05:58write to the um output register. You
1:06:01should be able to read from the output
1:06:02register. You should be able to read
1:06:03from the input register and you should
1:06:05be able to write to the um
1:06:08uh control register and read from it as
1:06:10well.
1:06:12All right. And then we'll go through it
1:06:14together. All right. Go for it.
1:06:20Did you miss one?
1:06:22>> Of course.
1:06:23>> No, I lost my uh my my purse here.
1:06:27>> Oh, go look.
1:06:29You need one.
1:06:31>> Sure. Uh, I don't know.
1:06:34>> Yeah.
1:06:36You need more up there? Oh, yeah. They
1:06:37need a whole bunch up there. Okay.
1:06:47>> They need it. There we go.
1:06:49Being stingy with them. I should have
1:06:52pass it down.
1:06:55Oh, here. Just take that. There you go.
1:06:57You guys need some. Thank you.
1:07:09There you go. I suppose you need one to
1:07:12there. Okay.
1:07:38No,
1:07:54[clears throat and cough]
1:08:07>> [clears throat]
1:08:08>> You have to draw.
1:08:20>> All right. So, this is what the the
1:08:25manufacturer says. the data sheets that
1:08:27that the ports have to do these things,
1:08:31right? So from basically if you look
1:08:34through data sheet, you will see a bunch
1:08:36of port definitions and registry
1:08:38definitions and then you can think for
1:08:40yourself what should be in that chip.
1:08:42What have to be there? So here we know
1:08:45that there is at some uh memory location
1:08:48some address 48008
1:08:51there is a register in and you can only
1:08:54read from it.
1:09:11There's a pin missing for data in the
1:09:14path. You can describe
1:09:20No, this
1:09:31morning
1:10:08All right.
1:10:25[clears throat]
1:10:36Yeah.
1:11:03SMB.
1:11:17Bless
1:11:39you.
1:12:07Now
1:12:11that They're
1:12:27all
1:12:36right.
1:12:39Yeah.
1:12:51Yeah.
1:13:17Wow.
1:13:52I don't know.
1:14:02President
1:14:12[snorts]
1:14:28[clears throat]
1:14:41Is
1:15:05that
1:15:10position?
1:15:33Are you
1:15:46Holy name.
1:16:28>> [clears throat]
1:16:41>> So it's All
1:16:55right, let's go through the rest and
1:16:56see.
1:17:03>> All right, I saw lots of good answers
1:17:05out there. Let's see.
1:17:11All right.
1:17:13So, one of the tricks is these are six.
1:17:15You only need 16- bit addresses, not
1:17:1732-bit registers. It doesn't really
1:17:19matter, but uh because the data sheet
1:17:22said only need the lower 16. The upper
1:17:2416 didn't do anything. And now we got to
1:17:27figure out how to connect these up. And
1:17:28so, the data sheet also said that uh I I
1:17:31should explain this better that the
1:17:32motor was the control. And then we have
1:17:34output input. You have to be able to
1:17:36write to the output register of course.
1:17:38And you should be able to read from
1:17:40that. You have to be able to write to
1:17:42the control register of the motor and
1:17:44read out of it. But you only need to
1:17:46read out of the input register. So the
1:17:49so if you look through the data sheet,
1:17:50it tells you how it's connected to the
1:17:52ABB, right? You can like look through
1:17:54the data sheet to understand what the
1:17:56architecture underneath is. And so I can
1:17:58draw some of those lines here. Let's see
1:17:59what I did. So I took PR data, I
1:18:02connected it to those two.
1:18:05And then I took the output because I
1:18:08have to be able to read from all of
1:18:09them. And it shouldn't say 32. It should
1:18:10say 15 to zero. And then I didn't didn't
1:18:13explain this to you, but you would
1:18:14probably need to have a MX there to
1:18:17select which one of those should be read
1:18:19back when. And I didn't really prompt
1:18:20you on that one. So that you need a MX
1:18:22to connect it back to the output because
1:18:25you can't have three 30 or three 16- bit
1:18:28buses going back at once. Okay.
1:18:32And then what are we going to do? P
1:18:34clock no worries.
1:18:36Then we need to be able to individually
1:18:39select which register will the data be
1:18:42written into. So that means we have have
1:18:45to have to have a way to individually
1:18:48uh select uh individual peripherals or
1:18:51individual registers. So here we've got
1:18:53a mask on there and then we have a we
1:18:57also have our and in there. So all those
1:18:58have to be true and all that has to be
1:19:02true.
1:19:03such that I have to have P write, P
1:19:06enable, P select and the correct address
1:19:08to enable say the output register to
1:19:11latch in data that will be sent out to
1:19:13the output register.
1:19:18Um, and then you don't really have to
1:19:20worry about it, but there's extra
1:19:21control lines because when you are uh
1:19:24when you're reading from the APB is
1:19:25reading from one of these registers,
1:19:27that register has to be uh connected to
1:19:29the output uh bus.
1:19:33And then what else? Oh, then the output
1:19:36of the pin has to go to the input of the
1:19:39input register. Okay.
1:19:43And then the outputs of the GPO uh
1:19:47control register goes to the control and
1:19:49the output of the output register goes
1:19:51to the output or input pin I suppose of
1:19:54the uh pad.
1:19:57And then let's see. I forgot what what
1:19:59is

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