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EECS 373 - Fall 2026 - Lecture 4: “Memory Mapped IO / APB Bus — Transcript

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0:00begin. Uh let's see. So today we're
0:03going to be talking about memory mapped
0:05IO, which is kind of like a new concept
0:06you probably haven't seen in 370 before.
0:09Uh some announcements. So homework's due
0:11today. Homework 3 was posted and it's
0:14due next week. And then office hours are
0:16today right after class from 3 to 4. If
0:18people need extra office hours, they can
0:20let me know.
0:22Um
0:25yes pro to normal lab schedules
0:29right all right so talk about component
0:33of the day how many people know what
0:34voltage regulators are
0:38then you'll actually learn something
0:40fantastic for the rest of you so last
0:42time we talked about batteries why can't
0:44you just connect up a battery straight
0:46to your device what's the problem.
0:55You got your microcontroller. Oh, here
0:56we go.
0:58>> Drains drains over time. Which what is
1:01that? What's the implication for the
1:02electronics? Let's say it could tolerate
1:04that voltage range. What's the what's
1:06the challenge if it's changing its
1:08voltage over time?
1:14I saw I saw a hand. Somebody take a
1:17guess. You could be wrong. It's okay.
1:23Yes.
1:24>> Too low.
1:25>> Might get too low. Uh so yeah, it might
1:28get too low. So your uh electronics have
1:31a certain happy range which it was
1:33designed for. Usually your
1:34microcontrollers here are about 3.3.
1:36They might go up to like 3.5 maybe down
1:38to 2.7. Depends on the microcontroller.
1:41But internally, sometimes there's uh
1:43analog components that are expecting a
1:45certain voltage and especially like uh
1:48oscillators or digital oscillators,
1:50they're all expecting a certain voltage
1:52so that the timing works out. And if all
1:54of a sudden you give it some weird
1:55voltage, this might have some unexpected
1:57behavior or at least that behavior might
1:59change over time. So sometimes your
2:01device works one way, battery drains
2:03down, now you have a device that works
2:05at a different way. And one way to
2:07handle that is to have voltage
2:08regulators. So voltage regulators their
2:10job is to essentially as it would imply
2:13regulate the output voltage so it's
2:15stable and constant all times and it's
2:17really trying to solve a few problems.
2:18One is trying to reject noise and you're
2:20like well where does the noise come
2:21from? Well especially if you connect it
2:22to the power lines or something like
2:24main lines there's lots of noise on
2:26those but then even on the battery
2:27powered system uh you can get noise in
2:29the system and your voltage regulator
2:31helps with that. Um also it it allows
2:34you to take voltages that would be
2:36unsafe for your device. So say you had
2:38like a 9volt battery or something, you
2:41could get down to 3.3 volts with a
2:42regulator and now your device can run
2:44and operate safely. So regulators have
2:47this nice job of uh solving the problems
2:50that batteries have caused and unstable
2:52power sources have caused by giving out
2:54constant voltage. And the hope is that
2:57they will provide any amount of current
2:59the device requests. Right? The device
3:01starts booting up, it starts going
3:02faster, it starts absorbing more
3:04current. Well, the regulator's job is to
3:06try to provide that amount of current at
3:08the reg at the voltage. Um, things to
3:11think about is not all regulators can do
3:13all current, right? So, your regulator
3:15has a certain current range that it can
3:18uh supply. Uh, some of regulators have a
3:21fixed voltage. You look at the
3:22manufacturer's data sheet and you get
3:24one for exactly the voltage range you
3:25want. Other ones are adjustable. So,
3:27there might be a resistor on there.
3:29There's a little bit more versatile. Um,
3:31and then the maximum voltage input range
3:34is important to think about. Not all
3:36batteries or not all regulators are
3:38going to work with all batteries. So,
3:40anyways, you're designing your embedded
3:41system. You're thinking about power,
3:43thinking about batteries, uh, voltage
3:44regulators. The next thing you need to
3:46look up, any questions about voltage
3:48regulators?
3:54No questions.
3:57Okay.
4:00All right. So today we're going to move
4:01on. We're going to talk about memory
4:02mapped IO and then the basically the
4:04mechanisms that you that are used to uh
4:07implement it. So bus architectures and
4:09the advanced peripheral bus. So we can
4:11start off by remembering that ARM has
4:14set forth this memory architecture or
4:16this memory layout. You have code at a
4:19certain location SRAMM peripherals
4:23external memory
4:26external devices and systems. And so you
4:29may think that this all represents like
4:31SRAMM or some memory structure, but it's
4:35actually very I mean it does, but it's
4:37also very varied. So like the question
4:39is how does this structure map onto this
4:42architecture?
4:43And so what you find is that sure
4:45there's SRAMM and code goes into normal
4:49structures like flash and SRAMM and
4:51maybe the system goes up there but then
4:53you have your peripheral memory spaces
4:56actually in the peripherals and you have
4:58off maybe off the high performance bus
4:59or the low performance bus you'll have
5:01uh these extra addresses allocated for
5:05these devices
5:07and so if we look at the idea of this
5:09peripherals and and GPO pins we have the
5:12peripheral range here and that is
5:14representing that you can take and load
5:16and store data in and out of that memory
5:19block which represents something over at
5:21those addresses. So uh those oh yeah
5:23those ports have been updated for your
5:25uh microcontroller
5:27and so you can even look at the first
5:28one let's say and that really is a data
5:31storage mechanism that is you can put a
5:33word in there right um that has bits and
5:36it stores it but it's not again it's not
5:38SRAMM it's not uh a particular memory
5:42structure in this case it's going to be
5:43a bunch of D flip-flops and these d
5:46flip-flops are going to store that
5:47information that you've just put in
5:49there.
5:51Now, the trick and the idea behind
5:53memory mapped IO is that instead of
5:56saying that I'm going to have special
5:58instructions to do things like make a
6:00GPIO pin go high or low, I'm going to
6:02have a register or a memory location
6:06particular let's say you know this
6:074,0001 that represents the state output
6:10state of the GPIO and you're going to
6:11put a number in there and that's going
6:13to change the state of the output. So
6:16now we're going to have your
6:17microcontroller is just going to be
6:18using loads and stores and it can
6:20manipulate
6:21GPIO pins or timers or all these other
6:24functionalities
6:27that would be separate from portmapped
6:29IO. Um so portmapped IO would be like in
6:32an application pro processor like an
6:34Intel processor where you're going to
6:35have special instructions just to talk
6:37to video card or memory and they're
6:40going to be much more optimized but
6:42there's overhead with that. So ARM here,
6:44we're in the space where
6:45microcontroller, they're not trying to
6:46go for max performance. Remember ARM's
6:48business model is they don't want to
6:50support special instructions for
6:52everybody's peripheral. That wouldn't
6:54make sense. It would be too hard for
6:55them for every manufacturer to keep
6:56track of it. So they're going to say,
6:58"We're just going to use loads and
6:59stores." And then that's going to load
7:02and store information into some
7:03registers, some memory. And then the
7:05manufacturer is responsible for turning
7:07those loads and stores that data in
7:09there into some action, some GPIO
7:11output, input, whatever it is. And
7:13that's where you look at the
7:14manufacturers's or data sheet to figure
7:16out when you do a load into a particular
7:18or store into a particular memory
7:20address, what is the function that
7:21happens. Does that make sense?
7:27Oh, nobody has questions. that somebody
7:29was excited.
7:32All right.
7:36So, the goal of what we're going to try
7:38and teach you now is how you go from
7:41your registers to your GPIO or just and
7:43it could be any peripheral. It doesn't
7:45really matter. GPIO is just a peripheral
7:47like a DACK or a timer or Ethernet or
7:49any of those things. And so we're going
7:51to try and figure out how do we go from
7:53registers in our core and actually
7:55traverse
7:58all the way over here. What's the actual
8:00mechanism kind of like signal level that
8:02goes from there to there. Okay, that's
8:05most of what we're going to be teaching
8:06today. And then just to to give you the
8:09heads up, we're going to talk about what
8:10what is actually in a peripheral from a
8:12conceptual point of view because we have
8:14we have this bus. We're not going to
8:15worry about the high performance bus
8:17right now. Once you learn the per the
8:18the advanced peripheral bus, all the
8:21same learnings go to the advanced um
8:23high performance bus. It's just with a
8:25little less complexity. So here we're
8:27going to try to we're going to talk
8:28about the bus structure to get through
8:30here. And then what is actually in these
8:31peripherals? Well, here we see the bus
8:34is connected and conceptually it's just
8:36a bunch of registers. There's registers
8:37in there. Those registers happen to be
8:39at a particular address and you can
8:41store data into them and pull data out
8:43of them.
8:45And then we're going to talk about today
8:47is there's a bunch of like logic on the
8:48front of this thing. We're going to get
8:50through all these details that help the
8:52bus actually talk to those specific
8:54registers. Remember, there are lots of
8:55different peripherals on your device.
8:57And some of those peripherals have
8:58multiple registers. And so we need to be
9:00able to make sure the data gets to where
9:02it's supposed to be. And then any every
9:04one of those peripherals have some
9:05custom logic, right? So if it's a timer,
9:07it has these little timer modules that
9:08keep track of things. If it's an analog
9:10digital converter, it's trying to sample
9:12some analog signal. And most of what
9:14we're going to talk about for the next
9:15couple days is just going to be the idea
9:17of GPIO.
9:20And then sometimes, and in the case of
9:22GPIO, it's true. Then you're going to be
9:25able to actually affect something else
9:26outside the world. So here in this
9:28little conceptual model that just
9:30represents one of those GPIO pins that's
9:32on the outside of your board. Of course,
9:34if you had a timer or something else,
9:35you might not ever go outside. It might
9:37just be all internal inside your
9:39peripheral.
9:41What questions do you have? This was a
9:43lot of information. I'm sure I wasn't
9:45clear.
9:52>> Yeah.
9:59>> I'm sorry. Say that again.
10:06>> Yeah. So the peripheral here is going to
10:08have multiple registers. So you guys in
10:11lab were talking to a periphery, your
10:13GPO peripheral, right? And you were
10:14sending data into your let's see there's
10:16the configuration register, there's the
10:18output register, there's the input
10:19register, right? And so you might have
10:21multiple registers inside one
10:23peripheral. We're just talking about in
10:24this case this one set of registers for
10:26instance. And then uh then it's doing
10:29some tasks over here and controlling
10:31that pin. So like a peripheral is a
10:34concept of a unit of logic that performs
10:37a task with multiple registers in it.
10:42And from the core core's point of view,
10:44it doesn't know it exists. The core just
10:47thinks I'm putting loads and stores into
10:49memory. It just thinks it's really good
10:50at talking to memory. And it's you as a
10:53programmer and your IDE that have to
10:54keep track of the fact that this memory
10:56location actually means something else.
10:57It means set up the output direction of
10:59this pin.
11:10This is all in chip. All of this is in
11:13chip. Um, if we go back, that's a good
11:16question. Didn't really make it clear.
11:19Let's see if I go back here. So, this
11:21all represents things that are inside
11:22the chip. Okay. Um, and so we have a
11:26couple buses and then if you want to get
11:28off the device, then there's like a
11:30little GIO pin that will go off to the
11:32external world. The second half of the
11:33class we talk about how like with SPI
11:36for instance which is a serial
11:37peripheral interface protocol how you
11:39would talk to chips off device. So right
11:40now we're all in in device.
11:43Does that answer your question? Yeah.
11:46What else we got?
11:50Don't be shy because uh this is if I if
11:52I can clear up the confusion now it'll
11:55help you later on. All right. So
11:57anyways, we're getting to the point
11:59here. We're gonna try and send data
12:00here. we have to go through these bus
12:02structures and then into this conceptual
12:04GPIO or this uh this peripheral module.
12:09Uh so let's look at a slightly different
12:10example. So say we want to interface uh
12:13to external memory, right? We don't have
12:15enough SRAM on device and we want to add
12:17extra SRAM. Well, ARM has gone through
12:21and given us register or memory space
12:24and it says if you write to these memory
12:26locations and you configure connect this
12:28external RAM because it's external off
12:30device then we're going to be able to uh
12:34use this just as normal SRAMM. Okay. So
12:38my question to you is uh we saw before
12:40that that exists on the uh uh advanced u
12:45peripheral bus and how this little block
12:49here. How does the um uh so we have this
12:54device how do we actually take that
12:55memory address range and actually put uh
12:59data into here? What's what has to be in
13:01this peripheral block just conceptually?
13:04So why don't you take a minute and think
13:05about it like how would you how would
13:08this work? Are you going to store data
13:10into this and then it gets transferred
13:11over? What is that mechanism? What would
13:13have to be in that memory location? So
13:15why don't you take you know 60 seconds
13:17talk to your your neighbors figure out
13:19what would have to be in that peripheral
13:21block.
13:40I'll put that up for you. Keep talking
13:42though.
13:50[sighs]
14:12>> [clears throat]
14:15>> You guys are like dead today. What
14:17happened last weekend? Oh my god. All
14:20right. What do you think? What? Anybody
14:23got an answer? What what is in this
14:25thing?
14:27How would you do this function?
14:31Yeah.
14:42map. [clears throat]
14:44>> Yes, that's essentially what's
14:46happening. So, you're 100% right. Now,
14:47when you say, are there physical
14:50locations on device that map to physical
14:54locations off device?
15:00>> Okay.
15:02Would there be uh Okay. Anybody else?
15:06It's pretty good.
15:11Yeah.
15:26>> I think so. Now the question is
15:30let's say that's a gigabyte, right?
15:32That's as much space as it is. How many
15:34registers do you think they're going to
15:35be?
15:39not enough.
15:40So what we're saying is having taught
15:43the class a few times, you could
15:44interpret it this way. You could say,
15:46"All right, well, I know there's a
15:47gigabyte here because that's how much
15:49space is there." And so I'm going to put
15:51the data in here and then it's going to
15:52get transferred out device and then it's
15:54going to have the one to one mapping.
15:56What's wrong with that idea? Why won't
15:58that work?
16:02>> Well, say we had a gigabyte here and I'm
16:04going to take data from here. I put one
16:06gig in there and then I just duplicated
16:08off off device.
16:13>> What's that? Is it
16:16>> uh that's a you could be but uh STM or
16:21ARM has only given you one gig of uh
16:24address space worth of address. So
16:25that's as large as it could be. But
16:27what's the what would be the challenge
16:28with having a gigs worth of uh D
16:31flip-flops?
16:32>> Yeah.
16:40Yeah.
16:46>> Right. So, like unless there was
16:47somebody who's like, "All right, I have
16:48to have a thing where I like hot swap it
16:50off and on or I don't know what it would
16:51be, but that seems like a different
16:52problem." What's the other problem with
16:54having a gig of uh D flip-flops? Yeah,
16:57>> it's large.
16:58>> Yeah. So large in a sense that in in the
17:01IC world uh having memory takes up
17:04physical space and die the area of your
17:07chip is the cost function right so you
17:09want to make that thing as small as
17:10possible and on your particular uh
17:13device in lab I think it's only 325k
17:17of uh memory that's it on the entire
17:19device so it couldn't even there's not
17:20even room for a gig
17:23all right so that's the problem oh right
17:25352
17:27uh so we're not going to do that but
17:28instead Instead, what they're going to
17:30do is they're going to have a they have
17:31an external bus unit specifically for
17:33this which effectively emulates all
17:36those addresses. They aren't physical
17:38addresses in the sense of like there is
17:40a register to put things in. It just
17:42emulates any data that you would send
17:44in. You send it to this address range.
17:46It takes it and it forwards it over.
17:48Right? So, you have this little state
17:49machine in here that says, "Oh, I'm
17:51going to respond to this address and I'm
17:53going to store it over here." And if
17:54they ask for anything, then I'm going to
17:55go and look in external memory and pull
17:57it back. So really this becomes a little
17:59bus mechanism to talk back and forth.
18:02Now the core doesn't know that there's a
18:04bus inherently, right? The core is just
18:05like I'm putting memory in these
18:08addresses and this device is taking care
18:10of the rest. So now we have you might
18:12think about it is emulated uh registers
18:15or emulated memory. Um it's just
18:17physically backed you know this is
18:19another way to say it maybe physically
18:20backed memory but the uh locations don't
18:23physically exist but from a protocol
18:26point of view you can send data in it
18:28and it gets taken put into external
18:29memory. Yeah
18:32>> it's not I wouldn't use the term virtual
18:34memory because that has a specific
18:35connotation in uh processors but you
18:38could call it like maybe in the class of
18:40microcontrollers it would be like a
18:41virtual address or something.
18:43>> Yeah.
18:49Yes.
18:56>> How does a microcontroller or how does a
18:59uh
19:07>> this is for all microcontrollers in with
19:10this architecture. So um this is what
19:14ARM has laid out saying that it will
19:17support this architecture and then
19:19device manufacturers are free to
19:21implement underneath that however they
19:23want. So device manufacturers can't put
19:25SRAMM in external device space. I mean
19:29sure you could they could make a crazy
19:30machine that does that but uh the SRAMM
19:34has special IP path and DPath so
19:37instruction path and data path to
19:38optimize fetching from there and you
19:40won't get that same benefit if you put
19:42it up in external device space so the
19:45architecture says lay out all your stuff
19:47in this space you don't have to use it
19:48all but this is what we're going to give
19:50you
19:51>> then
19:55>> yes this is we are uh learning about the
19:58uh ARMv7-m
20:00architecture and so if you went to the
20:02application class processors yeah you
20:04can have many gigs
20:20>> um it's up to the device manufacturer
20:22for your particular devices I think they
20:24only do um the the bus structure that uh
20:28Infinion has provided you only does I
20:31think a quarter of a gig. That's as much
20:33as it can do. And they just didn't
20:35implement the bus to emulate more
20:38addresses.
20:42But I mean you could you could find
20:44probably a different product maybe not
20:45at Infinion but somewhere in the world
20:47that gives you the full gig. Is it?
20:56>> Uh, no. You can buy a gigs worth. I
20:59don't know why Infinion chose to do
21:00this. My guess is that they looked at
21:02the benefits versus the area and said,
21:04"Well, our customers don't want this."
21:06Like going for a full gig of external
21:08SRAMM is just not that important. So,
21:11we're not going to add the extra
21:12complexity and increase our diet cost
21:14for that trade-off.
21:21I don't know exactly because I didn't
21:23design it yet. But let's just imagine if
21:24you're able to handle uh larger and
21:27larger uh address spaces and we're going
21:29to talk about this a little bit later.
21:30Then you're going to increase your
21:32complexity of your bus system and you
21:34have to have more logic. So I'm sure
21:36it's just a design trade-off. I'm not
21:37sure why they chose it, but I can we can
21:39invent good reasons for it.
21:42What else we got? Yeah.
21:45Can you say that?
21:48>> Yep.
21:49So, um, in our toy example here,
21:53um, we're saying that the core is
21:56allowed to write data to all these
21:58addresses, right? But there's not memory
22:02on chip that represents it's at every
22:04one of those addresses, right? So,
22:06there's probably in there there's a few
22:08registers, right? There's a register for
22:10like load and store or like input in and
22:13out. and it says, "Okay, I'm gonna go to
22:16uh register one and it's going to go to
22:18set that's one register and then it goes
22:19I'm going to put it into the next memory
22:22location." Still the same register,
22:24right? It's just that this thing is
22:26pretending like it's a new uh address
22:29for for the core sake and the core is
22:31putting in sequential address reads even
22:33though it's the same thing because
22:34what's happening underneath is it's
22:35taking that data putting it off chip
22:37into SRAMM.
22:42>> Yeah. Yeah. and how the how big that
22:44buffer is and all that other stuff, I
22:46don't know. We can go look it up in the
22:47data sheet. But um from the core's point
22:49of view, it thinks there are addresses
22:51for each there's memory at each one of
22:52those addresses. It just doesn't know.
22:58>> Yeah,
23:04>> I would use multiple. This is a
23:07conceptual super IO pin. Um you probably
23:11I don't know. you're probably in an 8 or
23:1316 bit uh bus. Uh it depends on if it's
23:16parallel. There's there's a bunch of
23:18different protocols. So Quad Spy is one
23:20uh that they would use. That's a good
23:22question that wasn't clear. Any other
23:25questions?
23:28You guys are figuring out all the things
23:29I I forgot to tell you. That's great.
23:32Okay.
23:35Um All right. So, Methodon, what am I
23:37trying to teach here? Oh, basically this
23:39is just uh the big idea here is this
23:41loads and stores from the cores point of
23:42view. Um there's two basic ones I think
23:45about. There's like this emulated memory
23:47we just talked about, but there's also
23:49registers that exist in a peripheral. Um
23:52or it could be another place in there,
23:54but it's not like a me the focus of uh
23:58peripherals is not to be data storage
24:01per se. it is to data will represent uh
24:04some task that needs to be done and the
24:06core is just putting in data back and
24:08forth loads and stores but the
24:10peripheral is interpreting it as
24:12something else so that's like the two
24:13basic ways to think about memory mapped
24:15IO uh yeah and again it's just loads and
24:18stores okay and then I guess the other
24:20key is uh you know when you you're going
24:22to hear about some peripheral like
24:24that's and then you know be given some
24:26task that's really your call to start
24:28reading the data sheet in this class and
24:30then whenever you use it in industry
24:31Your data sheet is where it's going to
24:33tell you, okay, this peripheral has this
24:35functionality. Uh, it has these specs
24:38and then it'll tell you how to interface
24:40with it and which registers to put the
24:41data into to get some functionality. The
24:44ARM doesn't as a company doesn't know
24:46what's in those peripherals.
24:48Okay, so we're going to move on. We're
24:49going to talk about the bus structure of
24:51how we're transporting the data across
24:53the chip.
24:54So bus is just a set of wires and
24:57supporting circuitry and it's a protocol
24:59to send data back and forth between two
25:00locations. So one example would be a
25:02parallel bus where data in one clock
25:05cycle is sent across uh in this
25:08particular thing is eight bits across.
25:10Another type uh is a serial interface
25:12where multiple clock cycles data sent
25:14over. So we're thinking on chip. What do
25:17you guys think would be the type of bus
25:19structure that would be used?
25:28Why don't you take 30? Oh, go ahead.
25:30>> Why parallel?
25:43>> I think those are all true. I didn't
25:44think about the logic point. It is um it
25:48is much faster because you don't take
25:49time. And uh one of the things we'll
25:52learn about later on is that uh on chip
25:55it's easy to have parallelism. So you
25:57can have buses. It's when you're trying
25:58to get any information off chip that
26:00there's the real problem. You it's very
26:02hard to put a lot of parallel buses off
26:04chip because it just takes up uh GPIO
26:06pins. And you would think, oh, just put
26:08more on. You're actually getting really
26:10pin limited. The thing that limits
26:11application class processors as well as
26:13these little microcontrollers is you
26:15just can't have enough physical little
26:16bumps to have wires that come off chips.
26:18And then we have to invent things like
26:20serial protocols.
26:22So uh this is an example of um uh you
26:26know an Intel 88 here uh all the basic
26:31logic units right here we have carry and
26:33ad is old processor obviously with
26:35registers and stacks and then there's
26:38this bus structure underneath it and the
26:39bus structure here is uh partly it's to
26:42power provide data but it's also to ship
26:44or provide power. That's what uh the red
26:48and blue are. But the rainbow colors are
26:50there to actually that's the data path
26:52to send data back and forth between
26:54devices.
26:56Um one person asked me like why why are
26:59we making it so hard? Why do you need a
27:01bus structure? Just put the two things
27:03next together. Just run a wire. And
27:05that's okay. That's in a simple chip
27:07like that. Maybe you can do it and maybe
27:09that's essentially what they're doing.
27:10But the reality is when you have
27:11multiple destinations, how do you choose
27:14where the data is going to go? But you
27:15want you don't want to run a wire or a
27:17set of bus wires to every possible
27:19location. So a bus structure just
27:21becomes a necessary evil. It seems
27:23overly complicated what we're going to
27:24talk about today, but it's really hard
27:25to figure out an actual cheaper, simpler
27:29structure that would do the effectively
27:31the same job.
27:35Um, oh, I forgot to load this up, but
27:38um, you guys can uh look at false ad. So
27:41just to think through this, have did you
27:42guys in in 270 do bus structures at all?
27:47No. Okay. Oh, we'll do it. Um, let's
27:51see.
27:53Well, okay.
27:56Well, for the sake of time, uh, we're
27:58not going to show the default stat, but,
28:00uh, you can, uh, look play through this.
28:02Basically what's happening here is just
28:04a counter that counts up and then
28:06there's a bunch of D flip-flops and then
28:08on every clock cycle it transfers data
28:10over and then uh visualized here the B 0
28:14through B7 uh is this timeline
28:16underneath and you can just watch the
28:18counter pass data over and then the
28:20other one over there is just a display.
28:22It's a binary to to decimal display. And
28:25all we're just showing is you have a set
28:27of D flip-flops here happens to be eight
28:29of them. And on every clock cycle, it's
28:31going to send out whatever data is
28:32there. Whatever data comes out of the
28:33side is going to be transferred over to
28:35that side. That's just the big
28:37conceptual uh concept. Kind of like you
28:40learned about multi-stage processors
28:42where you had one set of registers that
28:43would pass data to the next stage. This
28:45is just uh for the function of passing
28:47data around the chip.
28:51Oh, and I I don't know why.
28:57Okay. Uh, so we're going to send data uh
28:59to different devices, right? And so here
29:01we're saying that in each one of these
29:03little blocks is a place where we need
29:05to send data. And so I want you to think
29:07work uh with your partners just kind of
29:09think about what are the signals that
29:10you would need other than data and
29:12clock, right? That if you need to
29:14transport data to arbitrary locations
29:15around the chip, what else do you need
29:17as part of that signaling structure? And
29:20uh the thing I should have motivated
29:21here is uh there's a clock and there's
29:23data, but there's other things that are
29:25needed. So take 60 seconds, think about
29:27what are the other structures or signals
29:29you're going to need.
29:56Next initiate.
30:17>> [clears throat]
30:22>> All right. What do we think? We got to
30:23send data from the core to all those
30:26different locations. What other signals
30:27do we need other than clock and data?
30:35Brave people. Who you?
30:38>> Well, we have a clock.
30:43>> I'm sorry.
30:46>> Uh, sure. That would be we want
30:48birectional data. Okay. So, now we want
30:50not only are we going to send data, but
30:52we have to send data back. So, we're
30:53going to need a different path.
30:57>> Interrupts. What would they No.
31:01Uh, but you'll learn about them later
31:03and you'll can tell me that was wrong.
31:04Okay.
31:06Chip select line.
31:07>> What's that?
31:07>> Chip select line.
31:09>> Chip select line. Uh so uh yes, we won't
31:14call it a chip select just because we
31:16are all on the same piece of silicon,
31:19but it would probably be helpful to be
31:21able to tell this peripheral
31:22specifically I'm talking to you. What
31:25else do we need?
31:29>> Yes. So we have addresses not only of
31:32just the peripheral but also of the
31:33registers in the peripheral.
31:36indicate.
31:38>> Okay. So, some control lines. Okay.
31:41Yeah.
31:44>> Oh, okay. Yeah, you guys may have been
31:46looking ahead in your slides. That's
31:48very clever. Okay. Let's see what we
31:50got. Um, so I said data. We're going to
31:52need address lines because there's a
31:54specific register that we're going to
31:56have to go to. Uh, control lines. So,
31:58that can be a select and enable. Um and
32:01then again the idea here is we're going
32:03to have multiple of these so that uh the
32:04data is going to go through to all of
32:06them uh or some signals are going to go
32:09to many of them. We may have a select
32:10line in particular. Okay, I think you
32:14guys got everything. Yep. Uh so in this
32:17world we have the terminology of
32:18requester and a completer. So requesters
32:21is just a thing that starts the
32:23transaction. Um there are ARC bus
32:26architectures where you could have
32:27multiple uh requesters or multiple
32:30masters you might say but in this world
32:32there's this one and that is essentially
32:34the uh APB bridge uh or the advant the
32:37high performance to uh peripheral bridge
32:40and then we have completers these are
32:42things that do the task that the
32:44requester has asked for. So they cannot
32:47initiate a conversation only the
32:49requester can but the completer does the
32:52task that's asked for. And so we can
32:54look through this example we have a
32:56store. So the core is going to uh you
33:00know execute this instruction and
33:02there's going to be some combinational
33:04logic that's basically looking at the
33:06output of the or the uh the cores lines
33:09right to say okay I recognize this is a
33:11store. It's this address and that
33:13address. And then there's some state
33:14machine here which is going to take that
33:16request and turn it into these logical
33:18lines which is going to transport the
33:20data across the device. And then you
33:21have to have a completer with some sort
33:23of uh state machine that's going to
33:25interpret that and then turn it into GPO
33:28pins. So this thing is trying to figure
33:30out you know I've got an address. Is
33:32that address in the things I care about
33:34the range I care about? It's got is it a
33:36load or a store? It has to generate some
33:38signals and transport some data. And
33:40then remember there's can be a completer
33:42is part is a peripheral let's say uh and
33:46it could have multiple GPO pins. So any
33:48one completer is looking for is this my
33:50address? Is it a loader store? Do I have
33:52to what task do I have to do? Is it
33:54asking for data?
33:59And then uh once the completer has been
34:02selected and it's responding correctly,
34:04then it might in any of the peripherals
34:07may have or almost always have more than
34:09one uh register in it. And then the
34:12address is selecting which uh peripheral
34:14address it goes to or register is put
34:16into.
34:17So any questions before we dive in.
34:22All right. So this is that was supposed
34:24to be high level. We're going to talk a
34:26little bit more details on the signal
34:27level. So before we talked about that
34:29there's this high performance bus and
34:31there's a low performance bus. We we
34:33shouldn't call low performance. The
34:34advanced peripheral bus. The peripheral
34:36bus and high performance bus are trying
34:38to do two different tasks. The advanced
34:41peripheral bus is generally lower power,
34:44simpler interface, but also very latent
34:47latency tolerant. If you have some
34:49temperature sensor or some Ethernet
34:52traffic that's really slow, the advanced
34:55peripheral bus can handle latency where
34:57the advanced uh high performance bus is
34:59really like I'm sending data to memory.
35:02I'm going to this external device maybe
35:04I'm using DMA where this is uh much
35:07faster uh and made to be deterministic.
35:10This also like a pipeline bus structure
35:14uh it can have multiple initiators or
35:17requesters with a DMA. So once you learn
35:19this one, you would have a you know
35:21enough to be able to read the data sheet
35:23and understand this. But we're not going
35:24to inherently teach this one uh in in
35:27this class. So, for the purposes of 373,
35:30we're going to be doing this. We're
35:32going to be talking about this interface
35:33here. There is a relatively short um
35:38manual. I don't actually expect you all
35:39to read it, but I think it's only like
35:4139 pages or so. So, if you had to, you
35:44could just not trust me and read the
35:45whole spec yourself. Yes.
35:56uh it's um it is
36:00very complex and so what we'll learn
36:03later on it's actually not even it has
36:05multiple requesters or multiple masters
36:07so and it has multiple lanes in it so
36:10you are able to control traffic from
36:13different devices so you may have DMA
36:15that's going to two different locations
36:16in memory while your core is talking to
36:19an ADC and so the complexity is high and
36:24I guess that would increase power
36:25consumption in area. So there is a
36:27logical reason to have both. Uh we did
36:30talk about I think on the first day that
36:33uh because Infinion is making um like
36:36real-time control hardware they actually
36:38have a uh their peripheral bus is a
36:42version of a high performance bus with
36:43some features taken away. So to your
36:46question, you could use either one. It
36:48just are you hitting your particular
36:49design goals.
36:53All right. So we'll talk a little bit
36:55about single notation. This is just in
36:57the data sheet and you'll see a lot of
36:58this um uh as we go through slides. So
37:02there's clock and then it's just showing
37:03you here are some transitions like
37:05transition from high to low. And this
37:07little gray area here is just saying
37:08that the spec is defining that there is
37:10some uncertainty. That's all it's
37:12saying. We don't really care and this is
37:14a a stable bus. We don't really care
37:16about the high impedance state or low
37:17impedance state. You may see it
37:19somewhere. And this is just showing that
37:20a bus is changing. Uh bus being that
37:23this would be a concatenation of
37:24multiple lines on top of each other. And
37:26that's why you see a top and a bottom
37:27where a single uh line could either be
37:30high or low. Okay.
37:34All right. So, uh we'll go through a
37:36bunch of signals. These are the signals
37:38that exist on your um on the advanced
37:41peripheral bus. You have a clock, right?
37:44Just one bit. Everything here is going
37:46to be clocked on the positive edge.
37:48There's the advanced peripheral address.
37:50So, this is the address of the
37:52registers. Okay, it's going to be uh in
37:55our world, it's going to be 32 bits.
37:57Then you have the pite signal. This is
38:00just binary high or low. And it's just
38:02defining is this a write operation or a
38:05read operation. And that's essentially
38:08the same as is this a store or a load.
38:10They could have called it store and
38:11load, but because it's its own spec,
38:12they're going to use a different
38:13terminology.
38:15Then you have a p data. There's also a
38:17read data bus. We'll show that later,
38:19but this is going to be 32 bits. And
38:21typically what you're shown is that
38:23there's um you know there's some data.
38:26And this is how we'll just we'll put
38:28some hex value here or hex value here
38:30just to indicate that uh there is data
38:33there and what that data would be.
38:36So one caveat. So the P address is
38:39probably not 32 bits wide in the real
38:41world, right? It's a good teaching
38:43mechanism for 373, but think about what
38:45you need to do. The the P adder address
38:48line only needs to have enough bits to
38:51cover the possible peripheral addresses,
38:53right? So it's unlikely you're going to
38:56have 4 gigabytes worth of uh peripheral
38:59addresses. It's going to be some smaller
39:01number. And so the what happens is that
39:04in this little state machine you have
39:06your address space. The core is sending
39:09out some addresses and then the
39:11requesttor maps it to a subset of those
39:14uh those possible numbers into a P
39:17address space and you will never see
39:19that P address space on your little
39:21microcontroller or your IDE. That's
39:23abstracted away. It's important to kind
39:25of understand how the microcontrollers
39:28and this processors work. But just a
39:30caveat, there's probably not 32 bits. In
39:33fact, you can go in the um the data
39:37sheet and there's about uh 4,800 or so
39:40different distinct memory mapped
39:42registers in the peripherals. So, you
39:45don't need 32 bits to represent every
39:46one of those registers. You probably
39:48only need 13 bits. So here I'm just
39:50saying that in reality the address lines
39:53only is probably 32 or 13 bits wide
39:56because you just don't need to represent
39:57every possible address that the
40:00microcontroller could address. Um but
40:02for simplicity uh and what we're trying
40:05to do here we'll just say it's the
40:06memory address equals the P adder
40:08address. It makes everything a lot
40:10simpler. Just when you go into industry
40:12just remember that those are not exactly
40:14the same. They just don't need to be the
40:15same.
40:17I'm sure that was confusing. What
40:18questions you have?
40:26Yes. Thank you.
40:33>> Yeah, it's just it's just a visual
40:35indication that the bus had certain data
40:36on it and then we went to some other
40:38data and it's showing you that there is
40:39a transition that occurred.
40:44I appreciate the question even if it's
40:46not about the slide. At least I know
40:47he's engaged.
40:51All right. Uh then we have some other
40:53bus structures here. So or bus signals.
40:55So P select that is kind of like a uh
40:58chip select although it's on the device.
41:00And so P select is selecting the entire
41:04peripheral or the entire completer. Now
41:07remember that the completer itself uh
41:10can have multiple registers and multiple
41:12addresses inside of it. So basically
41:14you're saying here's this big logical
41:16block of uh you know combinational logic
41:19and I'm going to turn this I'm going to
41:21tell this entire thing okay I'm going to
41:23select you versus the other peripherals
41:25and then look at the particular address
41:27inside and I'll send you um some data.
41:31Okay
41:34P enable basically is enabling uh saying
41:38that the the transition is ready or the
41:41the bus is ready. So, we'll talk about
41:43this in a second, but there's a setup
41:45phase and then an execution phase or
41:47action phase. And the P enable says the
41:50data on the bus is ready for the
41:52peripheral to interact with. And P ready
41:54is a signal that's generated by the
41:56peripheral uh or we could say target or
41:59completer. And this indicates that the
42:02task it's supposed to do is done and
42:04it's ready to move on to the next thing.
42:07More precisely, well, we'll get to the
42:08next one. All right. All right. So,
42:10let's go through this example here. We
42:12have the setup phase. So, the address,
42:15you see that bus change symbol. It
42:17doesn't matter what the data was before,
42:18but the address has been put onto the
42:20bus. The right condition has been set
42:23either high or low. That indication
42:25there where it's double, that just means
42:27it's undefined. And then P select has
42:30gone uh high telling that particular um
42:33peripheral that okay, it's I'm talking
42:35to you.
42:37And then when those things are set in a
42:39setup phase, then P enable goes high
42:42telling the peripheral, okay, all that
42:44data is ready and T3 is your time to do
42:46action. Either I'm going to read data
42:48out of you or I'm going to put data uh
42:51into you. So it's your time to latch
42:53that thing in. And then P ready uh
42:56doesn't matter if it's high or low here.
42:58It's just saying it could be either.
42:59doesn't matter because it only is valid
43:02uh to for the uh uh the requester to
43:07think about or to measure when p enables
43:09high. That's the only time that's valid.
43:11So here it's saying I am ready and on t3
43:13it will clock in that data.
43:17So the spec is this two-phase. Oh it's
43:20uh set up and access phase. So you set
43:22up and then you access either at T3
43:26you're putting data in or taking data
43:27out.
43:31Uh, yep. And then you're latching data
43:32in. And then this would just repeat.
43:34Then you would go to the next one. You
43:35do another setup phase, another access
43:37phase. So maybe there's multiple reads
43:39to one peripheral or it'll go to a whole
43:42another peripheral. And then P select
43:43will be diserted. It'll choose a
43:46different P select, different addresses
43:47will be um uh put on the bus. Different
43:50data will be put on the bus.
43:54>> Yeah.
43:54>> So are you using the P select to
44:02Yeah,
44:06>> correct. So, so you could imag you could
44:09design this protocol to do other things
44:11as well. It's not like this is the only
44:12way to do it, but they're trying to be
44:14safe in the sense that there's a setup
44:16phase which guarantees the buses uh
44:18stable and then there's this access
44:20phase where data is actually latched in.
44:28And this slide just more for you guys
44:30just to have it written out what's going
44:32on. Um so here we'll do we'll wire up
44:35what it looks like for two devices here.
44:37So um every device gets there's one p
44:42data path which means the requester
44:44sends the same data to everything. Now
44:46we have to have control lines so that
44:48say completer one doesn't actually try
44:51to execute when it was completer zero's
44:53task and so uh we also have write and
44:57enable goes to every device as well.
44:59Those lines are shared.
45:03The address also goes to every device.
45:05Right? What's different is that every
45:08one of the completers or the peripherals
45:11has its own P select line. So there's
45:14one I guess I got my naming my numbering
45:16convention wrong here but P select
45:18should is going up to completer zero P
45:20select one is and P select 2 is going to
45:22completer one right so that is how it's
45:25telling this particular device now I'm
45:27talking to you even though the addresses
45:30are going to be uh there you know the
45:33addresses are going to be duplicated
45:35there could be multiple um resist or
45:37registers in there um so address alone
45:40is not enough you need to be selected
45:42and that's also just a way to like maybe
45:44the device is in power down mode or
45:46something in some other way and that's
45:47just a way way to select it and tell it
45:49I'm talking to you and then a clock is
45:52provided to all of them shared and then
45:55each one has a data path back. So the
45:59spec is a specification not a hardware
46:03um specification it's a protocol
46:05specification. So it says that uh each
46:07one of the completers and again there's
46:09going to be lots of them on your device
46:11has a data pass back that they can put
46:13data on whenever they want. There's no
46:15bus contention uh going back to the
46:18bridge. It's the bridge's responsibility
46:20to mx in the correct data uh to look at
46:23the right thing. So it's unlikely that
46:26there actually for everyone there's a
46:2732-bit bus going back there probably
46:29have MXes defined somewhere in the
46:32hardware. But for the purpose of the
46:34spec, each one of those has a 32-bit bus
46:37back to the uh the bridge or the
46:39requester.
46:48>> Yes.
46:59>> No, the hardware manufacturer does. So
47:01you as a user, this is um part of the
47:05class where like I need to teach you
47:07things that you'll never see, right?
47:09Otherwise, everything just becomes
47:11magic. That is one of the problems with
47:12this class is that uh we're in lecture
47:15specifically, I'm trying to teach you
47:16the low level so you can reason about
47:18how chips work for the rest of your
47:19life. However, the tools have gotten so
47:22complicated that they just wizzywig
47:23everything for you and then you just
47:25hope it works, right? And then it
47:26becomes to the point of like you'll get
47:28I I've certainly done this where I just
47:30trusted the tools to the point where
47:31they break and I can't get anything
47:32done. Well, hopefully this background
47:34will will help you reason through it.
47:37And then then you would go to like the
47:39GNU tools and you could get, you know,
47:41full control over every last little
47:43parameter if you had to.
47:46Any other questions? We're going to go
47:47through an example shortly.
47:50What? I must have missed something here.
47:52Oh, pre ready. Whoops. uh P ready. Each
47:55individual device has a P ready that's
47:57going to dictate when uh the completer
48:00is done with its task, right? When it's
48:02ready to move on. And we showed a two
48:05access phase or was it one setup phase
48:07and one access. We'll see later that the
48:10access phase could take longer. It's
48:12there's no requirement that it only
48:13takes one cycle.
48:17All right. So, let's Oh, and then
48:18specifically, I kind of showed this
48:20before. We're specifically talking about
48:21the interaction between the bridge here,
48:24the advanced high performance bus to the
48:27advanced peripheral bus. That is the
48:29requester and then the peripherals are
48:32the completers just to make it clear.
48:36All right. So let's go through an
48:39example here.
48:41Let's see.
48:44So what we're going to do here is we're
48:45going to have try and link code to
48:48what's happening on these bus
48:49transactions. So we have actually I'll
48:53send hand these out [sighs] get started.
48:55So I'm going to try let's see can you
49:01just pass one for your row here and then
49:03pass that up. Get one for your row and
49:06oh you're going to need more. Pass that
49:08up and then I'm going to deputize you
49:11for the whole front.
49:13And then
49:16if you could just pass this way and then
49:18up and then I don't know you guys can
49:21race. See what happens.
49:27Okay. So I'll set the problem up for you
49:29since you don't know what you're doing.
49:38All right. So assume we have multiple
49:39targets here.
49:42uh we have device one and device two at
49:45these particular address ranges and
49:47we're going to execute this code. So
49:49store
49:51uh the value that is in R0 to location
49:55R1 + 4.
50:02And then just to review what would that
50:04look like if we're looking at just the
50:05register in abstract memory? Well, here
50:08we have the the device the the the
50:12memory region for device one could say
50:14peripheral one and the memory region for
50:16per uh device two peripheral two and we
50:19have our registers and we have some data
50:22in memory so or in registers we have
50:241,00 and coffee in there and then we're
50:27going to do a store. So then we're going
50:29to do store the uh the value of R0
50:33that's located at R1 plus 4 and we're
50:37going to put it into this device. Okay.
50:39Right. So now we we see what's going to
50:41happen. We know the address of where it
50:42went and there's the actual the data
50:45that's been sent. And from that I want
50:49you to figure to draw in what must have
50:52been those bus lines,
50:55right? what signals occurred
50:58uh to actually that were sent across the
51:01APB to accomplish that goal was set up
51:04there.
51:42I'm on the right.
51:45[snorts]
51:55I don't know.
52:29>> [sighs]
52:45>> Thank you.
52:52>> [groaning]
53:04[snorts]
53:24>> Look at
53:43[snorts]
53:49[snorts]
53:50this one.
53:59I do not
54:20wish
54:49>> [clears throat]
54:50>> That's
54:51So
55:22>> [clears throat]
55:28>> That's fantastic. That's
55:47All right.
56:00>> [snorts]
56:02[clears throat]
56:11>> That's true.
56:22Here's
56:27what I think.
56:49Thank you. [clears throat]
56:51[snorts]
57:24That makes sense.
57:47I don't know what
58:24You can just
58:32Expressing
59:12All right.
59:28Thank you.
59:55All
1:00:07right.
1:00:19Oh yeah.
1:00:49I think you're ready.
1:00:57Are you ready?
1:01:08[clears throat]
1:01:38>> [groaning]
1:01:50>> Brotherhood.
1:01:55[clears throat]
1:02:11All right, one setup. I should have made
1:02:13it a little bit more clear. Oh, now it
1:02:16says P. This is I don't know why it says
1:02:18P now. The slides got away from me. But
1:02:20we have device one or peripheral one,
1:02:22device two. This is the signals that
1:02:23that device sees. That's what you're
1:02:25supposed to be drawing. I should have
1:02:27made that clear, but uh I think I saw
1:02:29some great answers out there. So, let's
1:02:31get started. What is uh address?
1:02:35>> Oops, I gave it away. What's the
1:02:36address?
1:02:380x 4
1:02:41>> four. Exactly. Right. Because we did
1:02:43post indexing like or indexing right
1:02:46there. Right. So it's it's incremented
1:02:48the address. And so both devices are
1:02:50going to see the same thing. So if we go
1:02:52over here, this is kind of like your
1:02:55guide. This is a this is the guide. And
1:02:58we get to see address is goes the same
1:03:01address goes to all devices.
1:03:04Okay. Same data goes to all devices.
1:03:07It's only certain signals that are
1:03:09different per device and then those
1:03:11devices react differently. Okay.
1:03:19Okay. And then oh I gave it away but
1:03:21we're writing right because this is a uh
1:03:25store action. So data is going into the
1:03:27device and then that is shared. How
1:03:31about P select? What's P select for Oh,
1:03:33you have a question.
1:03:35How do we how do we know when
1:03:43>> well okay so for so the specification
1:03:46always starts at T1 T0 this the diagrams
1:03:49not the actual spec so you just always
1:03:51see it this way and for whatever reason
1:03:53the diagrams always just start on T1 I
1:03:55don't care when if you guys wanted to
1:03:57put it at T3 you could but you're going
1:03:58to have to draw some extra lines because
1:04:00you won't have enough for the access
1:04:01space so the exact time occurs doesn't
1:04:03really matter
1:04:10Ah, so we're going to assume this is a
1:04:13two cycle interaction. Um, we didn't
1:04:16give you enough information
1:04:18for you to know all things. We just know
1:04:19that there's a register that's going to
1:04:21accept some some data. So now we're
1:04:23going to have a a setup phase and then
1:04:25an access phase. We'll learn later that
1:04:26there's got there's these weight states,
1:04:28but yes, you did not have enough
1:04:29information to know every aspect of
1:04:32this.
1:04:34Okay. So, what what is what's the P
1:04:37select line for P1 or D1?
1:04:46>> Yeah.
1:04:51>> Sure. But and how is that contrast to
1:04:54device 2 or P2?
1:04:57>> This low. Right. So that's one of those
1:04:59signals that's different between uh all
1:05:03every peripheral gets their own select
1:05:04line. And so here we're saying everybody
1:05:07got the address but P select selects
1:05:09that particular device. So here we saw P
1:05:12select go high in the setup phase which
1:05:15I arbitrarily chose to start at T1. And
1:05:18now that that peripheral is going to
1:05:20respond.
1:05:22Uh everybody gets P enable. Okay. That's
1:05:26just all that is is a signal that says
1:05:28the setup phase is done and now you're
1:05:30in the access phase.
1:05:33What about pite data? What's p data?
1:05:38I think I heard it or somebody was
1:05:40coughing. What are the two?
1:05:51>> What is it the same for both?
1:05:53>> Yep. Same for both.
1:05:56And then P ready.
1:05:58I guess I I underspecified what P ready
1:06:00is.
1:06:02But what do you think P ready does?
1:06:08>> Yeah.
1:06:13>> Yeah. So we expect that P1 P ready is
1:06:16going to be high at some point. It
1:06:18doesn't actually matter what P2 ready
1:06:21line does. Um, and here we're just
1:06:23showing it could be either thing.
1:06:25There's the only time that's valid. It
1:06:28only really matters what P ready is is
1:06:30when the device has been P enabled.
1:06:32That's it. Other times it doesn't
1:06:33matter, but at least then we knew it was
1:06:35high and then that T3 data was clocked
1:06:38in. So coffee gets clocked in. Now those
1:06:41people who took like uh 270 or thinking
1:06:44about setup and hold time and all that
1:06:45other stuff, don't worry. This is just a
1:06:47specification, not a hardware
1:06:48engineering documentation. Yeah.
1:07:00high again.
1:07:01>> Uhhuh. So why did it go low? Uh well,
1:07:05first of all, uh P select is only only
1:07:07matters when it's enabled. And then here
1:07:11what I didn't explain it well yet is
1:07:13that P uh the P ready is defined by uh
1:07:18the peripheral and it just says I have
1:07:20clocked the data in this next cycle. The
1:07:22data is clocked in and then it's ready
1:07:24to for the next instruction. Did that
1:07:26answer your question? Maybe you asked
1:07:27something different.
1:07:30And so we have to have the setup phase
1:07:32and then the access phase. The access
1:07:34phase we'll see could take longer. Uh
1:07:37but then that would be controlled by the
1:07:39peripheral.
1:07:40>> Yeah.
1:07:45>> We are making that assumption.
1:07:47>> Because that's the only thing I've
1:07:48taught you so far. So I was I should
1:07:49have been more clear about that.
1:07:54>> Yeah.
1:08:02>> Um why is P right? I think it's because
1:08:05pite does not matter. This is just their
1:08:07documentation but uh p doesn't matter
1:08:10because uh it doesn't have to be defined
1:08:13at that stage. P select has to be
1:08:14deasserted. P select should only go high
1:08:16when the device is actually selected.
1:08:19But you're right, there's no reason why
1:08:20P write couldn't be some other data.
1:08:22It's not like it has to be that.
1:08:35Why? P1 was the one that went high
1:08:38because when the um requester or the
1:08:41bridge was interpreting the memory
1:08:44access codes that came from the uh
1:08:47controller or from the core, right? When
1:08:49it said this is the address I want to go
1:08:51through, it looked up in that address
1:08:52range and said this address range resp
1:08:55is to device one or P1 and therefore I
1:08:59should only select it. Then it's because
1:09:00the address matched that range.
1:09:05>> Yeah.
1:09:16Is there high transition and uh
1:09:19impedance change
1:09:20>> impedance change
1:09:23uh the impedance change here is in the
1:09:26middle
1:09:27right and that is essentially saying
1:09:29that which is a case we probably will
1:09:31not discuss is when the bus disconnects
1:09:34through triates disconnects from the
1:09:36like the device disconnects from the
1:09:37from the bus and the bus impedance or
1:09:39the data is undefined it's undriven
1:09:43>> uh so I would not worry about high
1:09:44impedance or high impedance to stable
1:09:47does that answer your question.
1:09:49>> Yes.
1:09:50>> Okay. You can ask it again in the better
1:09:52way that I understand.
1:09:55>> Okay.
1:09:56>> Ah, yes. That's probably the best answer
1:09:58I could have given. Don't worry about
1:09:59it. I should probably just I was lazy
1:10:02when I copy and pasted that. I could
1:10:04just like uh I know crop that out. All
1:10:08right. How are we feeling? Any other
1:10:09questions?
1:10:11>> Yeah.
1:10:13>> What does bus stable mean?
1:10:15bus stable just means so those gray
1:10:17parts are the transition and you're just
1:10:19saying that the the data is defined then
1:10:25all right so if I wanted to review this
1:10:28problem I would think through some of
1:10:32like these diagram like read this slide
1:10:35come back read this slide to figure out
1:10:37what's supposed to be happening in here
1:10:39and then knowing where the signals go
1:10:42this diagram is is uh describing how
1:10:44those signals move around. And then uh
1:10:47the part I didn't explain well was just
1:10:50that um
1:10:53these signals are from the inputs to the
1:10:56peripheral. This is what the peripherals
1:10:58read. That's what this diagram is trying
1:11:00to show you.
1:11:02All right. Any other questions?
1:11:09>> Yeah.
1:11:13ah P uh enable it says um that the
1:11:19device or the the data on uh the bus is
1:11:23stable and now we're ready to go into
1:11:25the access phase. P ready is the only
1:11:28signal that comes uh in this diagram is
1:11:31the only signal that comes from the
1:11:32peripherals. Later on we'll see examples
1:11:34where data comes from them and that is
1:11:36the response. That's that kind of hand
1:11:38shaking that says okay I'm ready to
1:11:39clock in the data. I'm prepared to do my
1:11:42task.
1:11:49>> T1.
1:11:53>> So T1 to T T T T T T T T T T T T T T T T
1:11:55T T T T T T T T T T T T T T T T T T T T
1:11:55T T T T T0 to T T1 is just dead. There's
1:11:57nothing really going on. The only thing
1:11:58we care about is T1 to T2, which is a
1:12:01setup, and then T2 to T3. And then this
1:12:04is the next setup for the next cycle. So
1:12:06we just go back and forth between setup
1:12:08and access.
1:12:11Yeah.
1:12:23>> Yeah. Um, P select has said you are the
1:12:26device that I'm talking to. So, device
1:12:28one, it does not matter. And that's kind
1:12:31of what the diagram is showing you. It
1:12:32doesn't even matter what P Ready is on
1:12:34device 2. The the um requester is not
1:12:37going to listen to it. is not selected.
1:12:49>> Correct. Yep. [snorts]
1:12:51Yep. Yeah. And there's no U. If we go
1:12:55back here,
1:13:02um, it could definitely be the case
1:13:03where you have a peripheral that's just
1:13:05taking a long time and it's known to
1:13:07take a long time and it's going to
1:13:09collect its data and send data out when
1:13:11it's ready and the requester could go
1:13:13and do other tasks, right? And then then
1:13:16it will go look to see if P ready has
1:13:18gone high. Oh, it's finally high. Fine,
1:13:19I'll take the data out of out of this.
1:13:21So, there's a lot of things that are
1:13:22slow. temperature reading is slow.
1:13:24Talking on serial buses is slow. All
1:13:26these things are slow. So it just is a
1:13:29basically you can imagine it's an
1:13:30interrupt to the requester that says
1:13:32okay now uh this thing is done.
1:13:40What other questions do we have? Yeah.
1:13:53Correct. Yep. You can only read and
1:13:55write to one peripheral at a time. That
1:13:57is the difference between um the high
1:14:00performance bus and the peripheral bus.
1:14:02The high performance bus lets there's
1:14:04multiple what they call lanes or
1:14:06channels. So multiple transactions can
1:14:08occur. The peripheral is just one
1:14:10requesttor to multiple uh completers and
1:14:13just one at a time.
1:14:17All right.
1:14:18Let me get through one or two more
1:14:21slides and then we can call it. Um, all
1:14:24right. So, what's inside? What's
1:14:25literally inside these things? We talked
1:14:27a little bit about it. There is a bus
1:14:29interface, right? There's the bus,
1:14:31there's some bus logic and then there's
1:14:34uh some custom logic that thing is
1:14:36doing. So, we'll kind of go through that
1:14:37example. So, here we have an external
1:14:40LED that we're trying to light. Okay.
1:14:43And the prompt of this is say I want to
1:14:45control an LED which is connected to a
1:14:47GPO pin a single GPO pin um with the
1:14:51lowest significant bit of this 32-bit
1:14:53register. So how this is that kind of
1:14:56front matter. How do we get this
1:14:57peripheral to respond to the correct
1:14:59addresses and the and the correct bus
1:15:01traffic. So first we got to wire it up.
1:15:04So there's a lot of wiring. So we got P
1:15:06write data now all 32 bits because
1:15:08that's a 32-bit register just because
1:15:10it's set it and I use some nomenclature
1:15:12here where I have the little uh zero
1:15:14through 31 and this bus slash shows it's
1:15:1632 uh wide and then I have to connect
1:15:20the output of that to this uh to this
1:15:22GPO pin which happens to be connected to
1:15:24LED and I'm going to denote that it's a
1:15:26single line and I'm going toote that
1:15:28it's a zeroth line a zeroth register
1:15:31output
1:15:33P clock is going to go
1:15:35I mean there are technically different
1:15:36ways to architect this but we're just
1:15:38showing you one example. So here what
1:15:41has to be true for this have to be true
1:15:42you'd have to have right would have to
1:15:44be high enable would have to be high p
1:15:46select would have to be high and the
1:15:49correct address I haven't defined what
1:15:50the address is but you could use an
1:15:52andgate uh here we're just looking at
1:15:54the lowest eight bits so I don't have to
1:15:55draw 32 little bubbles
1:15:58and then if both those are true then
1:16:01we're going to enable the uh d flip-flop
1:16:04here or register bank to accept new data
1:16:07into it without that enabled down you
1:16:09know the enable is always high then
1:16:11every clock cycle will take whatever
1:16:12data is on the bus but we have to only
1:16:14enable that to accept new data when
1:16:17those conditions are met
1:16:19and then in this particular case because
1:16:21we know the architecture this will
1:16:23happen immediately so P ready can be
1:16:25held high immediately at all times just
1:16:28because we know this will execute on the
1:16:30first access phase there's no reason to
1:16:32wait
1:16:36how's that
1:16:39Do you think that logic would work? Do
1:16:41it satisfy the timing diagram?
1:16:45>> Yeah.
1:16:52>> Uh the purpose is I didn't define an
1:16:54address but it purpose is just to mask
1:16:56out a particular address. So this
1:16:58register is located at some location.
1:17:01Yeah. And uh and you could imagine a
1:17:04peripheral with multiple 32-bit
1:17:05registers and then you'd have to turn on
1:17:07each individual register.
1:17:11>> All right, we'll go through one more
1:17:12slide and I'll let you guys go. Maybe
1:17:14two more slides, I don't know. So here's
1:17:16the example with multiple registers.
1:17:19Um we have two and then there's
1:17:21different addresses ranges. So reg a
1:17:24should only respond to 1,00 reg B should
1:17:27only respond to 1004. These are in the
1:17:31same peripheral. So P select can no
1:17:33longer make that selection for us. P
1:17:35select just says this peripheral should
1:17:37turn on. So we need some other mechanism
1:17:40to enable this to tell which register
1:17:43should be uh enabled to accept data.
1:17:47So here we'll use the same mechanism. We
1:17:49can use a simple andgate. Now we'll have
1:17:52two different uh adders.
1:17:55And uh you can see that I was very
1:17:56clever and I have one bubble missing.
1:17:59I'll give you a better mechanism so you
1:18:00don't have to do this on the exam but
1:18:02there's this one bubble missing and now
1:18:04we're going to say when these is true
1:18:06and these things are true then we're
1:18:07going to enable that and the contrary is
1:18:11when this is true and this is true this
1:18:13is going to be enabled so basically you
1:18:16have to be writing the uh uh peripheral
1:18:20has to be selected enable has it has to
1:18:22be enabled to get to the top one it has
1:18:25to have the right address or and if you
1:18:27want to go to the bottom one it has have
1:18:28to have the right address. It could be
1:18:30some other address. And if it's not one
1:18:32of those two, then nothing will happen.
1:18:34Okay?
1:18:36Then uh data is going to come in 32 bits
1:18:38wide. That's what's going to get clocked
1:18:40in. If all those things are valid, those
1:18:42get clocked in. And in this particular
1:18:44case, because it's just a register, it
1:18:46can do this in one access cycle. It does
1:18:48not need a wait state. It doesn't need
1:18:50anything longer. So P ready can just be
1:18:52pulled high.
1:18:59Yeah.
1:19:09>> Oh, why is there a bubble weird bubble
1:19:11logic there? So, that's trying to mask
1:19:13for four. The other one's masking for
1:19:16zero.
1:19:17And then the last slide I'll show you
1:19:20here is when we when you do your
1:19:22homework or there's exam I just try to
1:19:23make some easier notation for you. So
1:19:25instead of doing bubble logic which is
1:19:27horrible. Don't do bubble logic. I can't
1:19:29read it. You can't write it fast enough.
1:19:31Just write down the word and add or mask
1:19:33and just write down the thing you're
1:19:35masking for in binary and that'll make
1:19:37it easy for me. Or you could do it in
1:19:38hex. I don't care. Uh and then these are
1:19:41the different versions of d flip-flops.
1:19:44They all you know you can have ones with
1:19:45enable. You could have reset if you
1:19:46want. You could take reset away. And
1:19:48then please on your homeworks and your
1:19:50exams to tell us how big these lines
1:19:52are. Right? So eight bits. If you're
1:19:55going to split lines apart, tell us
1:19:57where the bits go. And then you get
1:19:59logical.

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