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EECS 373 - Fall 2026 - Lecture 2: “Instruction Set Architecture (ISA)” — Transcript

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0:00can begin.
0:02So, let's see. So, announcements,
0:05class websites,
0:07um, yeah, Piaza is the best place to ask
0:09questions, of course, Grade Scope. So,
0:12make sure you're all on Grade Scope and
0:14specifically in the correct lab section.
0:16I know some people move, some people
0:18move outside of whatever Wolverine
0:21access. Uh, talk with James about that.
0:23Um, but make sure you're in the correct
0:25lab section. Your due dates are based on
0:26that. And then uh we have no canvas
0:28because canvas is lame. Uh homework.
0:31Homework one was assigned last night. Um
0:34the first bit of it is a bunch of analog
0:36review. That is intended to be all the
0:38analog you actually have to understand
0:40in this course. There's almost nothing
0:42to calculate. There's a little bit of
0:44like how do you buy a or how would you
0:46calculate a resistor? We give you a
0:47tutorial. So if you finished that
0:50homework assignment, you feel
0:51comfortable with analog, you're great.
0:52That's that's most the rest of the
0:53class. Maybe a few other examples. If
0:55you're having trouble with it, come to
0:56office hours. Uh my office hours, we'll
0:58have uh because we have a holiday on
1:00Monday, I'll have extra office hours. Do
1:02I have it on here? Yeah. Uh Tuesday at
1:0711 if you want, but you can also go to
1:09open lab hours. They can answer those
1:10same questions there. Um yeah. And then
1:14you still guys still have lab this week
1:16and prelabs are normally due before the
1:18lab, but this week labs will be due,
1:21prelabs will be due in lab. Are there
1:23any logistics questions before we get
1:25started?
1:29Somebody's got a question. Can't be that
1:32clear.
1:36No questions. All right. Um, get
1:40started. I often want to talk about I
1:41give it like a component of the day,
1:43right? And so these are connectors. And
1:45the goal here is to make sure that
1:46everybody has a general idea of certain
1:48embedded systems topics. It's not really
1:50lecture material, but if you don't know
1:51it, you don't know what you don't know.
1:53And so, uh, connectors are super
1:55important. And almost anything that you
1:57want to connect, two boards together,
1:58two wires together, a wire to a board, a
2:01battery to something, somebody's already
2:02solved that problem for you. And if you
2:05know the right connector, you're golden.
2:07And connectors come in lots of different
2:09shapes and sizes for all sorts of
2:10different reasons. There's probably two
2:11aspects you should know about, and those
2:13are uh connectors that are keyed. And
2:16that's in the sense that they can only
2:17go in one direction. and connectors that
2:19are locking. They have a little latch
2:21and you can't pull them off. And why
2:22this is important? So, when I was at
2:24Disney, I was mentoring a PhD student at
2:27ETHZurk. We had a sister lab there and
2:29those uh PhD students were basically
2:32almost full-time employees at Disney and
2:34doing their PhD studies and I was
2:36mentoring this person and they got a
2:38reputation for lighting the lab on fire.
2:41Okay. And we had an executive from parks
2:43and resorts come and they were doing
2:45this really cool work on body channel
2:46communication. say a little embedded
2:48system here, embedded system on the
2:49floor and all these objects and it would
2:51send electromagnetic waves along the
2:53body. So when you touched objects or
2:54stood on objects, the that
2:56infrastructure would know and you could
2:57send messages back and forth, but it
2:59wasn't like radiating everywhere. So it
3:00was being able to control data basically
3:02by touch. And so as Disney people, we're
3:04like, "Oh, we can build some cool
3:06interactions that way." Well, the big
3:08executive comes doing the lab tour,
3:10right? This student's a little bit
3:12nervous. They plug in their stuff.
3:14Literally, the floor catches on fire.
3:16They had all these tiles, floor tiles
3:18that would light up when you talked with
3:19them or when you walked over them. Why?
3:22Well, they were a computer science
3:23person, right? They had never seen the
3:25idea of keyed and locking connectors.
3:26They were just using 0.1 headers, like
3:28the most basic thing you could have in
3:30the world, this sort of thing. And it's
3:32really easy to make a mistake. So, if
3:34you didn't know that there was keyed and
3:36locking headers, you you just would
3:38never know to use it. So, here you guys
3:39here you guys know, uh there are
3:41different types of headers. Figure out
3:43what they're used for. And when you're
3:44facing a problem in the lab, especially
3:46project time, come and ask James or one
3:48of the IAS if they have the specific
3:49type of headers rather than trying to
3:51roll roll your own. And if uh this is in
3:54your uh note or your slides, but if you
3:56want more information about all the
3:58variations on headers, there you go.
4:01Any questions about headers
4:04pins?
4:06Guys don't have many questions today.
4:08All right. So from last week, uh what
4:10did we talk? We talked about embedded
4:12systems where it's going a little bit of
4:13class overview and a high level
4:15architecture of um your devkit and how
4:20the ARM core that thing basically the
4:22core what you learned in 370 and how you
4:24would actually get data out to the GPIO
4:26pin. And so today we're going to talk
4:29about the ISA for ARM and that's really
4:31the instructions you know the assembly
4:33code the register structure and the
4:35memory and we're going to try and talk
4:36about how all these work together. Some
4:38of this is definitely a review from 370,
4:40but we're going to try and highlight the
4:42differences for this particular
4:44architecture. Like what are the nuances
4:45and the catches that you'll have that
4:47will trip you up if you don't know.
4:49Okay, but it is more or less conceptual
4:52review. All right, so a little
4:54background on ARM. Oh, sorry. We'll
4:57start out with a background on ARM
4:58instruction set architecture, some
5:00specific instructions, and then we'll go
5:02through uh an in-class problem. So ARM
5:05is a company and they they claim that
5:08you know what is this 250 billion
5:10devices have been shipped. That's pretty
5:12good market penetration, right? That's a
5:14lot of devices.
5:16But they are a fabulous
5:19semiconductor manufacturer. What is a
5:21fab? How can a fabulous semiconductor
5:23manufacturer ship 250 billion devices?
5:32physically themselves.
5:35>> Yep, that's exactly it. Why? But why why
5:38would they do that? Why why wouldn't
5:41somebody else this why would somebody
5:42else take that design? What would be the
5:44value?
5:46>> I mean,
5:52you don't just simplify design. You
5:54know, you don't want to redesign a core
5:57instruction set. Makes things easier. It
5:59makes it easier to implement. like
6:01connecting stuff.
6:02>> You're getting the right ideas. There's
6:04a slight twist, but you've got the right
6:06ideas. So, uh they do as a company, they
6:09make the instruction set architecture.
6:10They make intellectual property which
6:12other people buy, right? So, who buys
6:14that stuff and they license that to chip
6:16manufacturers. So, who buys it? So, STM,
6:18Infinion, which is used in the dev kit,
6:20you have NXP and Texas Instruments,
6:22those are all kind of like the
6:23microcontroller. Then big companies
6:25right the application side like Apple
6:27and Samsung they all make uh they use
6:30those ISAs and then modify it they they
6:32add something to it or they add
6:34something to the chip. So Apple clearly
6:36is modifying maybe the instruction set
6:38architecture a lot itself but the other
6:40companies are going and adding something
6:42extra and that's the peripherals. So
6:44when we looked at that black diagram,
6:46it's those all those extra pieces
6:47they're adding. And so now to
6:50differentiate Infinion in the
6:51marketplace from STM, STM's maybe a
6:53little bit more consumer electronics
6:55grade. Uh Infinion is a little bit more
6:57on the control architecture like
6:59robotics and and automobile. So the
7:01peripherals have to do a different job.
7:03Infinion adds their intellectual
7:05property there. Uh but they still get to
7:08use uh all this other stuff here. So
7:10back to this question, why would Texas
7:13Instruments and NXP want to use the same
7:16architecture as everybody else? What is
7:18their business advantage? Why are they
7:20doing this?
7:24>> Yeah,
7:25>> there are tool chains that already exist
7:27for architecture like GCC has their own
7:30AR and stuff like that, right? So it's
7:32easier to write software and use
7:34software that's already been written.
7:37>> Yeah. Any other good reasons?
7:41Yeah.
7:44>> Sorry.
7:48>> They don't have to cover the cost of
7:49making chips. Is that what you said?
7:51Well, they still they still on the hook,
7:53right? Uh so STM has to fabricate the
7:56chip, sell the chip, and then they just
7:58kick back money as licensing fee to ARM.
8:02So they take on all the risk.
8:05Why not have why not just spin your own
8:07architecture?
8:09What's the disadvantage in that?
8:18>> Yeah. So, making processor designs is
8:21hard and complicated and you could spend
8:23years, you know, making a chipset and
8:26then, oh, you found out all these little
8:27edge conditions. You forgot that now you
8:29have to recall devices. Like, it would
8:30take a long time to mature a chipset
8:33architecture to the point where it would
8:35match ARM. So if you're going to enter
8:36the market now, boy, it's a lot easier
8:38just to pay ARM and get something that's
8:40solid, right? Something that's really
8:42well battle tested. Plus, there's a
8:44hidden value. So that's like the that's
8:46like the first draft value of for a
8:48company is saying, well, I can buy this
8:50thing. Sure, it's costly, but I I don't
8:53have to roll my own. Also, you can go to
8:55the other companies and get those
8:56engineers. Those engineers already know
8:58ARM, right? So when they come, it makes
9:00that the workforce is a little bit more
9:01fluid. So maybe that's good for the
9:02worker. Maybe that's good for the
9:04company.
9:07Um so ARM generally makes three
9:10families. So there's the cortex a which
9:12is the application uh class family.
9:14Those are like the smartphones and smart
9:16watches and those sorts of things. You
9:18have the real time which is for um like
9:21high reliability systems where you need
9:23to have some guarantees of certain
9:25performance in a certain time. So like
9:26braking systems for instance have to
9:28work all the time and there's guarantees
9:29of when it has to work. It can't get
9:31stalled by some other process. And then
9:33there's the Cortex M family which we're
9:35studying here which is microcontroller
9:37class but this is general purpose uh
9:39embedded system devices. And then
9:42oftentimes you'll see this confusing
9:43diagram. It took me about you know
9:45teaching the class one or two times
9:46before I fully understood this diagram.
9:48But this is how ARM says this is our
9:50this is our product line. These are all
9:51our ISAs. Well what they're really
9:53saying here is they have chipset
9:55architectures on the top and then they
9:57have instruction sets on the bottom.
10:01And specifically we are going to learn
10:03the ARM V7M architecture
10:07and that is instantiated as embedded
10:11systems in Cortex M4, M3 and so on and
10:14specifically of the ISAs that are
10:17available. We're going to look at thumb
10:182.
10:20So what is an ISA? So this is an
10:22abstract model of the computer defines
10:25how the software is controlled by the
10:26CPU and this really is in this agreement
10:29between you as the programmer and the
10:31hardware engineers and saying like if I
10:33do this instruction the hardware will
10:35obey it. It will complete this task.
10:38Uh so the ISA defines instructions, data
10:41types, storage, you know memory regions,
10:44addressing scheme, data flow control and
10:47ARM has uh multiple ISAs as you saw
10:50before. The two biggest ones are 32bit.
10:53They call it thumb and arm. I'm not sure
10:55why it's actually thumb and arm. Maybe
10:57it's because ARM is bigger than thumb. I
10:59don't really know. Um, and then for
11:02reasons we'll discuss, they came up with
11:03a hybrid system which is oh, and thumb
11:06is supposed to be 16 bit. ARM is 32. And
11:09they came up with this hybrid system
11:10which is thumb 2 which has 16- bit and
11:1332-bit instructions. And that's uh what
11:16we'll be using in this class.
11:19And then the differences between the
11:21hardware architectures, how it's
11:22instantiated is we have like cortex m0
11:25which are these little tiny little
11:26microcontrollers uh M3s, M4s and those
11:30are all concatenations of different
11:31instruction sets. So the Cortex M0 only
11:35does a subset of what the Cortex M4
11:37does. And then the the Cortex M4F has a
11:40floatingoint module. So that adds on
11:42some extra functionality.
11:47Uh so the architecture defines how the
11:49instructions are to be processed on the
11:50hardware. Uh again for us we're doing uh
11:53ARMv7 and implementing the thumb
11:56instruction. Um now thumb two
11:59instruction set. Now if we consider like
12:01cortex m the application a processor
12:04also implements the uh uh ARM v7m
12:09instructions and so does the cortex m4.
12:12They both do the same thing. It's just
12:13that the hardware instantiation is
12:15different. So uh the uh A8 is a 13
12:19pipeline uh processor while the ARM uh
12:22Cortex M4s are usually three stage
12:24pipelines. So this is I want you to get
12:27your head around the difference between
12:28instruction sets and architecture and
12:30how um essentially there there is some
12:33fluidity between there and they're not
12:34100% there's not one instruction for one
12:36architecture. Yeah. And they both run
12:38ARM Cortex M2. Any high level questions
12:41so far?
12:45No questions today. Oh, good. Brave
12:47person. You have to be loud though.
12:49>> Is there like a specific reason?
12:57>> Um,
12:59so
13:00well you you take 370, right? You guys
13:03learned a five stage, right? And so that
13:05allows you to do like it's been like 10
13:07five years since I taught that class,
13:09but I think you guys learned about like
13:10pre-fetching and prediction and all
13:12those other things. So there's all these
13:14other optimizations you get with
13:16multiple stages, right? To get higher
13:18throughput and the that's really good
13:21for an application class processor
13:22because you want this performance and
13:24you're willing to give up a bunch of
13:25things. You're willing to give up power,
13:27right? Because now you have to support
13:29the architecture of 13 stages. the M4 or
13:33the Cortex M4, which only has three
13:35stages. They're like, "Well, we don't
13:36need to have a graphics card and all
13:38these other functionalities. So, we're
13:40going to reduce the capability, but
13:43we're going to gain simplicity. We're
13:44going to gain lower power." So, it's
13:46there's a hardware engineering trade-off
13:48that was made. It's a good question, but
13:52no, I don't actually actually know all
13:53the stages of the 13 p stage pipeline. I
13:56just know it has 13. Um, so one of my
14:00question might be like why are there 16
14:03bit and 32-bit? Why does thumb have a
14:05mix? And it's kind of helpful to think
14:07through some of the architectural
14:08changes that have happened. So here's
14:10this maybe a throwaway image, but this
14:13is shows the evolution of they had their
14:15proprietary stuff that was ARM one
14:17through three which I don't even know
14:18maybe this was 16 bit and then they
14:20started with 32 and 16 bit now they have
14:2264-bit architectures. So independent of
14:26microcontrollers, what was the big
14:28architectural shift? Why were we moving
14:30from 16 bits to 32-bits to 64-bits?
14:33Especially like I think it was like 2000
14:36early 2000s there was in the PC market,
14:39right? There was a big shift from 32bits
14:41to 64 bits. What? So my question to you
14:44and I'll have you discuss it. What was
14:46causing the shift? Why was the industry
14:48keep increasing the number of bits in
14:50their architecture? And then conversely
14:52um what was the impact on the on the PC
14:55or the microcontroller market and why
14:56would they want to go and have a hybrid
14:591632? What would be the advantage? So
15:01why don't you take 60 seconds try and
15:03figure out why the industry kept on
15:05increasing the bitwidth.
15:17Yes.
15:39This is
16:00What do we think? What was causing the
16:02shift for larger and larger bit sizes or
16:06bit
16:06>> widths?
16:17It's true. Say it slightly differently.
16:26>> That's true. Definitely true.
16:36>> Yeah. How about memory? You you had you
16:38had all the right ideas for the memory
16:40but maybe a little bit backwards.
16:44>> And then so they added all these
16:47instructions more information
16:49instruction
16:51like memory that is term.
16:55>> Okay,
16:56you're all circling the right answer,
16:58but I'll just say the memory part. um
17:00the size of your instruction dictates
17:03how much physical memory you can address
17:06without doing paging or some weird
17:08thing, right? So you'll see that with 32
17:11bits, you can only get to about four
17:12gigs of memory. That's it. And so the
17:15industry wanted they're like, "Oh, well,
17:17you know, we want to get to larger bits
17:19or memory sizes." The applications
17:21demand it. So they went to 64-bit
17:23architecture so they could were able to
17:25index larger physical memories. That was
17:28a big PC push. Okay.
17:31What has that meant for the um
17:33microcontroller market? Why why would
17:36the microcontroller market not just go
17:38to 64-bits too? Why what why are they
17:42trying to optimize for the 16 bit and
17:4432-bit architecture at the same time?
17:53>> 16 bits. So they just use that but they
17:56want allow indexing in larger memory
17:59regions in addition to operation of
18:03>> that's pretty good right so 32-bit gives
18:07you a lot of flexibility in what you can
18:10uh in memory reads and writes and what
18:12you can address and people said it
18:14before
18:16um
18:18uh with 32 bits you can cram more uh
18:20functionality in one instruction but you
18:23pay a penalty right your code size is
18:26larger
18:27So now they're trying to optimize
18:28because they know these are little
18:29constrained devices. They don't have
18:31gigabytes of memory or um really large
18:34hard drives, right? You might be in
18:36SRAMM or flash might be like 150 or 128k
18:41of flash or something. It might be
18:42small. So now you have to optimize for
18:44code size as well. So the 16- bit and
18:4632-bit hybrid gives you a flexibility of
18:48both.
18:51Okay, that's what these answers are. So
18:54we'll move on to the instruction set. So
18:56the reason I told you all that is so you
18:58have to understand why have they made
19:01the instruction and the architecture
19:03this way well if you understand that ARM
19:06is a fabulous chip company right and
19:09they sell architectures they can't
19:11specialize in architecture for every
19:13single manufacturer right imagine if
19:16they had to create special instructions
19:18so this these are the peripherals right
19:20this is what STM and Infinion they make
19:24their intellectual properties here So,
19:25Infinine's going to have a a different
19:27say USB peripheral or a better ADC than
19:30somebody else. Who knows? Now, ARM, who
19:33makes the core over here, they don't
19:35want to have to be responsible for
19:37keeping track of what every single
19:39vendor is doing. That would just be
19:40impossible. I have to make in a special
19:42instruction just so Infinion can talk to
19:45their ADC and then STM has to have a
19:47different instruction. That's insane,
19:49right? It's just too much to do. So the
19:51goal here is once you understand that
19:53they're selling architecture then you'll
19:55understand why we're going to use this
19:57load core load store structure and how
20:00uh that has impacted the architecture.
20:02So that's why I I kind of gave you that
20:04background.
20:06So here we're going to talk about the
20:07ISA. Um you know that there's these lots
20:10of these bus structures. There's all
20:12these different locations. We talked
20:14about uh flash and and SRAMM. And then
20:17uh inside the peripherals there's
20:19registers or basically memory
20:20stateholding devices that the core can
20:22talk to to configure the USB or send
20:25data over that. So there's all these
20:26different addresses. But from the core's
20:29point of view, everything is just
20:31unified. There's just one in uh memory
20:34space. It doesn't know the difference
20:36between um inherently it doesn't know
20:39the difference between say uh memory or
20:41SRAM and a and a peripheral. it just
20:44loads and stores and they abstract that
20:46to the IDE or the compiler to keep track
20:49of this vendor's specific um uh
20:53peripherals and making sure that uh the
20:56code that's executed would be uh or
20:58compiled would actually execute
20:59properly.
21:01So ARM goes through and it mandates a
21:03certain memory structure. So it says hey
21:05there's 40 there's four gigs of space
21:08okay and it says okay your code is going
21:10to take up half a gig your SRAM's going
21:12to take up a half a gig peripherals
21:14external memory external devices and
21:17then they have some system stuff right
21:19so they have the private uh so we saw
21:21those buses there's bus error handling
21:23uh infrastructure there and then some
21:25system infrastructure so ARM says this
21:27has to exist right
21:31uh it's all unified uh memory structure
21:34from ARM point of view.
21:37Uh, yep. And so the other part that's
21:39nice is there's lots of interoperability
21:41here. So if you always know that
21:44peripherals are on this area, then um or
21:47or code is in these specific spots, then
21:50when um you know ARMs, you're going to
21:52implement say your uh your instruction
21:55fetch versus your data fetch, you can
21:57optimize that hardware for those
22:00regions. uh rather than having to say
22:02okay well this vendor put code up there
22:04right so it makes their system
22:05interoperable with all these other
22:07vendors there see questions or this
22:09yawning stretching okay
22:14so this is your particular device
22:17um unfortunately uh one of the things
22:20this is actually uh uh Infinion's memory
22:24map description it's not very complete
22:26there's lots of missing information this
22:28is almost what ARM gave you so you have
22:30to kind of dig into the tables to see
22:31some more information. So, uh, for
22:33example, ARM says that there's a half a
22:35gig for SRAMM, but the STM, this
22:38particular variant that you're using
22:40only has, uh, 352K. So, you have to kind
22:42of dig into the documentation here, and
22:44you start seeing this, right? You start
22:46saying, oh, here's my SRAMM space, and
22:48they've said they have their PS RAM and
22:50two DS RAMs, and they've assigned memory
22:53locations for these things, and
22:55everything else is reserved. What does
22:56reserved mean? Anybody know?
23:00Take a guess.
23:04Reserve does not mean it's for somebody
23:07else. Reserve doesn't mean that it's
23:09there. Reserve means it is not there.
23:11They have not implemented the memory.
23:13Right? Because memory equates to chip
23:16size. Chip size is cost. So they're not
23:18going to go and allocate four gigs on
23:20your device but only allow you to have
23:22access to 352K.
23:25That doesn't make any sense. So what
23:26they do is say okay I'm going to put the
23:28memory at these locations ARM told me to
23:30do that I'm going to do it dutifully but
23:31I don't have to implement all of it and
23:33that's where you see reserve reserve
23:35means there is no structure there you
23:38compiler will not let you actually load
23:41data in and out of it does not exist yes
23:45>> you got to be loud because I'm oldicular
23:48method
23:53>> so it's all in the documentation this
23:55particular table is not great, but you
23:57would start reading through your
23:58documentation and it's much more of a
23:59positive case where it says this uh
24:02peripheral lives at this address space.
24:04It doesn't actually tell you where
24:05there's nothing, but it tells you where
24:07things are. So for you can just assume
24:09that unless it's already stated there is
24:11no state memory device at those
24:13locations.
24:15>> Yeah.
24:16>> If there's no like if there's nothing
24:18like implemented on memory, then what's
24:20the purpose of
24:22>> ah why why even do this? And so that
24:25goes back to this interoperability
24:27problem, right? So, uh, ARM has stated
24:33that your code and your SRAM must go in
24:35these locations. Okay? Uh, but they
24:39never said that it has to be a certain
24:40size. So, if STM even even Infinion will
24:45have different devices will have
24:47different amounts of RAM, right? But ARM
24:50doesn't know what they've implemented.
24:52So rather than say you could take this
24:53whole table and collapse it down and
24:55remove all the the um uh reserve point
24:59so it's only used memory but then all
25:02the addresses would be different for
25:04each chip and now all the infrastructure
25:07that the ISA is giving you such as like
25:10the instruction path and the data path
25:11and all these other things would be
25:13would change breaking this
25:15interoperability of the ARM
25:16architecture.
25:18What happens when you try to access
25:20those?
25:22>> Uh so you will get uh it will be
25:24undefined.
25:26A good uh microcontroller would probably
25:29at least give you all zeros or some
25:31known pattern and your uh IDE or your
25:35compiler should throw an error and say
25:36you should never get there. But this
25:37would be out of bounds would be a common
25:39error.
25:40>> Are there protection
25:42for that or is it freak out?
25:44>> It's going to probably freak out.
25:45There's there are not great protections.
25:48Let's say that.
25:50>> Y
25:55>> what's sorry SRAMM where where
26:04>> I don't know. We have to go look it up
26:05in the data sheet. Don't know. You guys
26:08are going to You guys are going to know
26:10more about the data sheet. So you just
26:11switch this thing. You'll probably have
26:12more eyeballs on the data sheet this
26:14semester than I will. So you guys can
26:16tell me afterwards. Um,
26:18but I if I had to remember, I don't
26:21know. Uh, I have no idea. I have no idea
26:23what it's for. I have to We really
26:24should go look it up. Any other
26:26questions? Yeah.
26:31>> There's no memory. Is that always logic
26:33behind me?
26:36>> There's is there logic behind what
26:38>> which of me or is it random or how do
26:40they choose?
26:41>> Uh, the vendor chooses. They choose
26:44where they want to put memory. Now, it's
26:46best if you have you kind of play an ARM
26:48schema, right? So, ARM says that code
26:51space should start at 0000, right? They
26:55say the SRAMM should start at 2000. So,
26:57it's unlikely they're going to start at
26:592000 something, right? They're always
27:01going to start at the base probably and
27:02move their way up.
27:05But, it's really the vendor that has to
27:06keep track of where they've put things.
27:15Uh yeah, and then you can go add this up
27:17and actually see that it does add up to
27:19the stated memory on the device. That's
27:22all it that's all the SRAMM there is.
27:26Okay.
27:28So again, ARM is going to treat this as
27:30a unified memory from the chorus point
27:32of view when you're writing assembly or
27:34even C. There's no inherent
27:38reason why you would know that one uh
27:40memory location has the functionality of
27:42storing bits while another memory
27:44location has the functionality of uh
27:47enabling your your USB controller,
27:49right? That's put on you to remember or
27:52uh your compiler and your IDE to
27:54remember that these other
27:55functionalities are there. That would be
27:57different than like say something like
27:59portmapped IO uh which you would think
28:02about with like an x86 architecture
28:04where it's like the north bridge and
28:05south brid bridge. Those um ports aren't
28:09general purpose. They're specifically
28:11optimized for memory or video and they
28:14have in individual instructions to
28:16optimize just for those things. So
28:18rather than having instructions just for
28:21USB or your ADC or your GPIO's, we're
28:24going to use a general purpose
28:25instruction that you have to as the
28:27programmer keep track of functionality.
28:32Okay. Uh so we can talk about the the
28:35organization of memory. So memory each
28:38memory location has a 32-bit address and
28:40each address uh holds a bite of
28:43information. So it's one way to
28:45visualize it. Here we have addresses and
28:47you have data in bytes.
28:50However, this is a 32-bit architecture
28:52and almost all the way we think about
28:54and use it is at the 32-bit uh level.
28:57Like we're going to store a 32-bit word,
28:58we're going to load a 32-bit word. So
29:01when I think about this, I think
29:03everything is 32-bit wides with a um
29:06memory that increments by four. So this
29:08is generally my mental model. We have
29:11addresses that increment by four. it
29:13just happens to be that you also have
29:16this extra functionality
29:18that you can um go in between right and
29:22just do bte reads and bite stores out of
29:24that memory. So this is this is maybe
29:27the most strictest interpretation of
29:29what uh the memory is allocated but this
29:32is probably how you should think about
29:33it with just having the ability to read
29:35out bytes and store bytes rather than
29:38just going after entire words.
29:42This does require you to know your
29:44endingness or endingness. Um and so it's
29:48good just to review the difference
29:49between little Indian and big Indian. So
29:52little little Indian is increasing
29:53numerical significance with increasing
29:55memory address. Um big Indian is the
29:58opposite. Thumb two architecture in ISA
30:01allows you to flip that on the fly.
30:03There's literally a flag you could flip
30:06to change to go to read data in big
30:08Indian or little Indian. And that is
30:10mostly about legacy code, right? So you
30:12have these other these C files, ancient
30:14C files, a part of GCC that were uh
30:18compiled for some reason and now you
30:20need to read those in. You don't want to
30:21reformat them. Uh then you can just go
30:23and flip the bit and have them read in
30:25big Indian if you wanted to. Uh for the
30:28purposes of 373, we're just going to
30:29assume everything's little Indian unless
30:30we tell you otherwise. This makes life a
30:32little bit easier.
30:35Any questions?
30:41You sure this is not confusing? This
30:43feels confusing.
30:47He This guy is so brave. I love it.
30:51>> Does memory exist?
30:53>> Nope.
30:56That's a good question.
30:58Okay.
31:02All right. Uh so that's your memory
31:04architecture. So there's uh and then
31:06we'll talk about your processor itself.
31:08that has registers 32-bit wide.
31:11Uh there's uh 16 of them. Uh we have
31:14their lower register, high registers.
31:15These are general purpose registers. We
31:17will talk about like R12 and R9 have
31:19special features when you talk about uh
31:21interrupts and some um uh other
31:25specialty edge cases, but we don't have
31:27to worry about that right now. You got a
31:28stack pointer, a link register, and a
31:31PC. There are two versions of your
31:33program uh or your um your sack pointer.
31:38They don't really come up in how we
31:40teach this class. You just might find
31:42that your compiler is doing weird things
31:44if you had to really dig into the code.
31:46At that point, just ask or read online
31:47what the difference is. It's basically
31:49the state of your um uh program whether
31:53it's the main stack pointer or the
31:54process stack pointer. Uh there's other
31:56registers like your um uh special
32:00purpose registers like the um I can't
32:02think of it. Oh, the program status
32:04register. Uh we don't really like the
32:06the prime the fault mask control mask
32:09and the base priority. We don't really
32:12worry about them right now, but there's
32:13a 32-bit um program status register that
32:16we'll have to keep track of. So those
32:18are the the main elements of your core.
32:22And then uh kind of an old diagram but
32:25you know as you start thinking about uh
32:27memory right you're gonna you have
32:29different memory locations and then it's
32:31good to think about how your code maps
32:32onto that. So in this world the stack is
32:35always at the top and grows down. The
32:37heap is at the bottom and grows up and
32:39heap is really only when you're doing
32:41like malo or calic for dynamic memory
32:43allocation. So here you could imagine
32:45those first two are dynamically
32:47generated and they grow up. um you have
32:51uh some things that go into the stack
32:54and then uh your code is usually in
32:56flash. Now the reality is it's not
32:59always flash. Often times what happens
33:00on boot is they take the code out of
33:02flash and put it into SRAM so you have
33:05faster uh uh code execution. Flash is
33:08permanent, right? It doesn't um doesn't
33:11lose state when you turn it off and turn
33:13it back on. Uh but it's pretty slow. So
33:15often times what happens is you're just
33:17not aware of it when you go to program
33:19your device for the first time. It will
33:21boot up and it will take all the
33:24instructions out of flash and put them
33:25into SRAMM and that's where it'll load
33:27out of but for the purpose of this slide
33:29your code lives in flash. Um yeah and
33:32then some you know some things might
33:33just be defined by the uh compiler and
33:36just instantiated in the registers.
33:41Um yeah, so we got registers uh we have
33:45uh locations for data right at the top
33:48which is this one big unified structure
33:50and then certain addresses have
33:51instructions in them. Okay.
33:59And so we'll talk about some
34:00instructions. So a little review 370 as
34:02you imagine uh there is an entire ARM 7
34:06architecture and you can go read up like
34:08for a move or a move s there is a
34:10certain instruction encoding. So this is
34:12an 16- bit example and you can go
34:15through and figure out how to do the
34:16encoding. So first you have these
34:18operands up front right those are
34:20defined by that indicates what the
34:22instruction is. you have a destination
34:25register. In this case, we're just going
34:27to say it's u zero. And then we're going
34:30to put some data into it, right? And
34:32here we have an immediate. So we're able
34:34to move an immediate into that register
34:36and we've decoded 10 into binary. So now
34:38you would take that and you put that in
34:40your code space in memory. And likewise,
34:43you can do the same thing for R1 or move
34:46s R1 u immediate zero. So here we have
34:49the same uh operand up in front and then
34:52the register is one and the data is
34:54zero. We're going to pack that into
34:55memory as well. And so ARM is nice in
34:58the sense that it allows you it's not
35:00just it it will pack the instructions as
35:02tight as possible. Yes.
35:06>> Not always zero.
35:07>> Register zero not always zero. What does
35:09that mean?
35:11>> Z.
35:12>> Oh
35:13your immediate. No, in some register.
35:23>> Yes.
35:25>> The the register name never changes. Are
35:28you saying it changes?
35:32>> Oh, no. No, it's not a constant. It's
35:34not a source of a constant. Um register,
35:37those are all dynamically changeable.
35:38All 16 of them. Um the last three are
35:41reserved for special purpose but there's
35:43no like source of a zero if that makes
35:45sense. Um the the primary way we get
35:48constants is is e is using moves. Use a
35:51move to move that thing in. So through
35:52an instruction
35:57uh what else? Yes. Okay. And then uh so
36:01you have your your program counter,
36:02right? So you're going through and
36:04you're going to go through your program
36:06space and your PC is going to point at
36:08something, right? It's got some address
36:09it's pointing at. It's going to pull
36:11that instruction out. We're always going
36:13to fetch uh instructions out of memory
36:16as 32-bit operations. So here we're
36:18going to pull out that 32-bit operate
36:20that 32-bit instruction. And if you're
36:22if it happens to be a 32-bit
36:24instruction, that's fine. You're just
36:25going to go through your pipeline as
36:26normal, right? Fetch, instruction,
36:27decode, and instruction execution. Fine.
36:30But if it happens to be two 16-bit
36:32instructions is it'll break it up. build
36:34say okay we'll do the first one and
36:36we're just going to save the second one
36:37and then start doing the execution there
36:39right so my question to you is uh when
36:42the core is fetching how does it know if
36:45it's fetching a 16 bit or 32-bit
36:47instruction so why don't you take 30
36:49seconds talks with your neighbor come up
36:50with some strategies
36:59I'm here.
37:31All right. How do we know? What would be
37:32a way for the core to know if it's 16
37:35bit or 32bit?
37:37>> Yeah.
37:41>> Yeah.
37:44>> Zes.
37:51instructions.
37:54>> Yep, that's a great way of doing it. So,
37:56here we have special codes, right, that
37:58only indicate whether this is a 32-bit
38:00or 16- bit instruction. So, what it
38:02does, it pulls it out, it looks at the
38:04first, it pulls out the 32-bit uh word
38:06out of memory, looks at the first five
38:09characters, decides if it's 16- bit or
38:1132-bit instruction, and then does the
38:13appropriate thing. So, the encoding
38:14space defines what it what it is.
38:18And then for you if you want to look
38:19through some of some more of the details
38:21they're here. All right. So let's think
38:24through a little bit how instructions
38:26impact uh registers. So uh you guys can
38:30tell me. So we have two different
38:31encodings. We have T1 and T2. You will
38:34look through if you look through the ISA
38:36there might be like for AD I think
38:38there's like 20 different versions or
38:40encoding just for AD, right? They're
38:42optimizing uh for something. So they
38:44have different uh codes or different
38:47encodings. And so here's a 16 bit and a
38:4932-bit encoding. So for instruction move
38:53s uh which is just a move and then
38:56you're going to set a status register
38:57flags R3 uh 15 which is put in immediate
39:01into R 15 into R3. Which encoding would
39:03you use?
39:13Can you talk to your friends? Yes. All
39:15right. Talk to your friends. Figure out
39:17what encoding you would use.
39:23[clears throat]
39:38>> All right. I heard reasoning. Somebody
39:40hazard a guess. Which one?
39:45First one. T1. Okay. You could use T2,
39:49but it would just be a waste of space.
39:51Right now, you're using up more program
39:52space. How about this? Uh, yep. T1. How
39:56about this? Which one would you use?
40:05>> Two. I saw two, right? Because 15 cannot
40:08be put into uh Oh, no. It's nine, right?
40:12R9 is not addressable. is not reachable
40:16uh from the uh destination register
40:18there. It would need four bits for that.
40:21All right. And then we can do this one,
40:24right? So move s uh 416 in decimal into
40:30R3 and we can just give away the hint.
40:32You can go look at the bit encoding and
40:34see that in fact that would have to be
40:37uh T2, right? because you cannot fit
40:40that value into
40:42uh that uh an 8bit immediate and they
40:45break up the immediates here. So you'll
40:47see there's an I here, there's a IM3
40:50here, and there's a IM8 here. And it
40:52shows you that the thumb expanded I am
40:56C. That shows you how these things are
40:58concatenated together. So they've spread
41:01the immediate across multiple bits in
41:03there.
41:04>> Yeah.
41:07>> What's that? advantage splitting the
41:11>> I I'm sure the fine engineers at ARM
41:13know exactly what advantage that is. Um
41:16I don't know. I I'm going to guess that
41:19they they have some ones here reserved.
41:21I'm going to guess that they need to
41:23have some ones there so that they can
41:24differentiate between maybe a 16 and
41:2632-bit architecture. I'm not exactly
41:28sure, but there's clearly some
41:30advantage.
41:34All right. So why does the ISA
41:37distinguish between high and low
41:38registers?
41:40Why is it making a differentiation
41:42between these? What? Yeah.
41:52>> Yep. So it does you could make up a M.
41:56So the argument here is that uh the most
41:58common instructions uh you would like to
42:01be small, right? So if you're going to
42:03do a lot of operations, the lower
42:05registers and we'll see later on that
42:07the lower registers are used for uh
42:09function calls and all sorts of things.
42:11If if you're going to call them a lot,
42:13you rather have those be small
42:14instructions. There's nothing keeping
42:15you from saying making a separate set of
42:17instructions that happen to only be able
42:19to get up to the highest registers in
42:21some weird fashion, but there's just
42:22less advantage of it. So the general
42:25thing is uh 32-bit instructions can get
42:27to almost all registers but 16- bit
42:29instructions can almost always get to
42:31the only get to the lower instructions.
42:35Okay.
42:37All right. So we'll go through some
42:39instruction encodings or some
42:40instruction types and we're going to
42:42plast through this because you took 370
42:44but this is more just to remind you
42:45these things exist. Okay. Um so there's
42:49you know there's aleric aleric and and
42:52logic functions. There's data move,
42:53there's branch and compare, and then
42:55there's a a bunch of miscellaneous ones
42:56as well. And so the question for you is,
42:58do you as a student need to memorize
43:00instruction codings? That would be
43:02horrible, right? And so when you did
43:04370, yeah, you had eight, right? For
43:06this instruction set, you could memorize
43:08them all. Uh ARM has 255. You don't want
43:12to, this is not worthwhile to memorize
43:14them all. It's not going to be valuable
43:15for your time, right? But but
43:19um you're going to want to be able to
43:20get through exam and homework problems
43:22fairly quickly. So uh on the website on
43:24the assignment page probably at the
43:26bottom there is a link to the reference
43:28card that we've made for this thing.
43:29You'll get this on the exam. If you get
43:31real excited uh there's also the
43:33official ARM two thumb to whatever um uh
43:37instruction card. I would make sure that
43:39you can read through this uh reference
43:41card quickly to get the information you
43:43need. It's rare that I'm going to give
43:45you some exotic function and like just
43:48hope that you can use it. But things
43:50like moves and loads and stores and
43:53branch conditions, you're going to use
43:55those all the time. So you might as
43:56there's some things that will be useful
43:58if you memorize them, but will give you
44:00everything on the exam.
44:03All right.
44:04I basically said the same thing that
44:06there are certain set of subsections
44:07that you want. Um and I'm just going to
44:10these are not even you shouldn't
44:11memorize these here. The the point here
44:13is just there's a standard set of
44:15instructions and then ARM does special
44:17thing where they make a version with an
44:20S on the end and S we saw that last we
44:22saw move s and s is this the pneumonic
44:25to update the program status register.
44:28So the output of an ad here will go and
44:31change the output of your SAT uh status
44:34register basically your ALU flags so
44:36that when you get to a branch condition
44:38or some other condition you can uh make
44:40a decision based on those uh program
44:42status registers right
44:47and so again you you probably seen this
44:50before but there's you know negative is
44:52it zero is there a carry right
44:54especially if you want to do like two
44:5532-bit instructions and add them
44:56together for a 64-bit it you have to
44:58know if you can carry there's overflow
45:00and other quantization flags and the
45:03program status register is actually a
45:06concatenation of multiples so you have
45:08your your ALU flags uh you have your
45:11interrupts and then you have uh we don't
45:13really talk about them but there's these
45:15IT flow control basically if you want to
45:17make fancy case statements there's
45:18another set of registers for that and
45:21those are all combined into the PSR so
45:23this is the program status register this
45:25is more or less holding the state of
45:27your processor. Uh if you call a
45:30function or need to uh do an interrupt,
45:34you're going to have to uh preserve some
45:36of the information in here. And we'll
45:38talk about that later. Any questions?
45:41>> Yeah.
45:42>> Why would you not want to update the
45:44programs as
45:46>> Oh, um maybe you just want to defer that
45:49decision later. So uh you could imagine
45:52a a program where the branch condition
45:55happens after some other computation and
45:57so by not updating the program status
46:00register you've saved that bit of
46:01information. In fact I had embedded
46:03systems project where uh that RFID tag I
46:06showed you on the first day um we were
46:08trying to read in this bit stream these
46:10edges from the RFID uh reader very very
46:14quickly and we just ran out of time. we
46:16just could not process them quickly
46:18enough. And so there was a little trick.
46:20We had one bit extra we had to keep
46:22track of. And all we did was we store
46:24that bit illegally, not illegally, but
46:25just nonsensically. We stored it in the
46:27program status register just so we could
46:30uh stay alive a little bit longer
46:31without uh losing track of state. So you
46:34could also just think about an emergency
46:35is you can store one bit there if you
46:37really had to. It may not make sense in
46:40the rest of your program, but it's it's
46:41a place you can update.
46:43Um, all right. The car classic carry
46:46example for time we'll just go through
46:48it. But the trick here is that uh by
46:51doing your ad. So you're going to add
46:53these two numbers together. You can set
46:54the flag with the s uh that will update
46:57it and then you can use your carry add
46:59functionality and then the it will look
47:02for the carry bit as you do it. And now
47:04you can do a 64-bit uh operation.
47:08Okay.
47:09There's bit w bitwise logic operations.
47:12So, ands and ors. Um, why would that
47:15matter for embedded systems? So, often
47:18times you have a register like your
47:20output port with a bunch of LEDs on it
47:22and you don't know what the other
47:23programs other parts of your programs
47:25have done if one LED is high or low or
47:27whatever. So, here you can just use this
47:30logical operation. You can read in the
47:32status of your register. Now, it's
47:34probably not 32 bits. It's probably only
47:35eight bits, but for this example, and
47:37then you can logically ore in the data
47:39you want. And now you're going to go and
47:41set that one LED that you wanted high.
47:43In this case, you wanted two LEDs high,
47:45but they're already there. And so a bit
47:46wise or operation is pretty useful. The
47:50contrary to that is the bit clear. So
47:52they give you a special function for
47:53that. Here we have a bit clear. And then
47:57you go through and you can say I only
47:59want to clear say the last four bits in
48:01this particular case. So now you have a
48:03way to manipulate bitwise uh register
48:07operations uh which just happens to be
48:10useful.
48:12All right.
48:14So uh there are moves. We talked a
48:16little bit about moves as a methodology
48:18for creating immediates. That's a common
48:20one. Obviously you can move things
48:22around registers. Moves don't move
48:23memory. That's what loads and store is
48:25for. So you can move data around your uh
48:28register. We have two special ones. So
48:31we have the the normal move immediate.
48:33So you move uh a number in and then we
48:35have move wide and move top special
48:38function. So move wide will go through
48:41and it will move in. So you can't you
48:44can't fit a 32-bit value in a 32-bit
48:47instruction. So the um the the uh
48:51architects have given you some
48:52functionality to allow you in two
48:54instructions to get a 32-bit value in a
48:56register. So move wide. What it does is
48:58it'll take the lowest uh 16 bits. It'll
49:01put it in there and it will clear out
49:03all the zeros. It'll clear out anything
49:05that was in that register. So like say
49:07R0, it'll make all that zero. And then
49:10move top only affects the top uh the top
49:1416 bits and then it will take 8765 and
49:18put that in the highest bits without
49:20perturbing the bottom. So in two
49:23instructions you can go and put in
49:25arbitrary values in your registers. But
49:27there's a challenge and if you do it
49:29backwards
49:31right here move top uh goes and will
49:35white and and there didn't know say it
49:37was a aaa it won't affect the bottom
49:38ones. Okay that's fine and you you've
49:40put your 876 in the highest bits but if
49:43you do move wide afterwards it has
49:45erased those bits. This is more like the
49:48logical ore here. This one is not. This
49:51one is um going to erase the top. It
49:54always instantiates that those must be
49:56zero.
49:58Any questions?
50:01>> Yeah.
50:01>> Is there another instruction that moves
50:05the 16 bits lower part?
50:10>> Well, moves it into lower while keeping
50:12the top part. No. No. um probably the
50:15closest thing you can do like logical
50:16shift lefts and that sort of stuff and
50:18then you could probably do a bit uh you
50:21could do an or functionality. So you
50:22still have to you're going to use
50:24multiple commands to get there.
50:30Uh yeah. All right. So then we have a
50:34load function. So load and stores are
50:36specific for memory for getting data in
50:38and out. So here we're going to take the
50:41the address that's stored in register R1
50:44and that's the memory address. And then
50:46we're going to uh take go to that
50:50address that's stored in R1 and take the
50:52value that's there in that memory
50:54location and put it into R3.
50:57And then there's just as 370 there's all
50:59the variations you could imagine. Uh we
51:01don't for us class we only really care
51:03about the standard loads and stores. We
51:05don't care about the unprivileged and
51:06the exclusive uh exor or loads and
51:10stores. Um I doubt you'll run into them.
51:13But here we have 32-bit, 16bit and 8bit
51:16operations. Okay.
51:19And so now it comes back to our mental
51:22model of what is the memory
51:23organization. So the 8 bit makes sense.
51:25At a particular address I can load and
51:27store. As 16 bit I can do two at a time
51:30in that case. And then a 32-bit I would
51:33always kind of fall back to this mental
51:35model of uh of memory where you're
51:38putting in a 32-bit word in an in wide
51:41at a time. Uh you have special
51:44functionality for things like sign
51:47extended. So say I have a a
51:50word I have calculated it. I want it be
51:53sound uh sign extended. It will put it
51:55into a memory location and then add fff
51:57at the top to indicate that it's uh sign
52:00extended. Okay, so my question for you
52:03is why is there not a store variant a
52:07store sign extended? Why is it only
52:10really valid and useful to have a load
52:12sign extended in this architecture? What
52:14do you think? So take 30 seconds.
52:50I also
53:05What do you think? Why why would we have
53:08a sign extended load function but not a
53:10store function?
53:16I guess instruction
53:24[clears throat] two instructions instead
53:26of
53:27>> so but why not uh have a so store I'm
53:30going to store into the register
53:32>> right out of memory so why don't we have
53:35sign extend store
53:37>> so the two reasons are one you can just
53:39sign extend separately
53:41>> sure
53:42>> one is there's no point making number
53:47Well, no, this is storing it into a
53:48register, right? So, you could sign
53:51extend a number in the register. So, why
53:53would you do that? Maybe you would do
53:55like I don't know why you would do it.
53:57Uh
53:59uh I can't well maybe you have an 8 bit
54:01you take a 8 bit value you do and then
54:03you put it into a register and you want
54:05to sign extend it. Why is that not
54:08useful or valuable? Why would it not be
54:10implemented?
54:16Yeah,
54:16>> I have a question.
54:20>> So, um, good question. So, we have
54:23memory and we have the core, right? And
54:25so, load and stores is our way to get
54:26data in and out of the core from memory.
54:29So, we're going to load data from memory
54:32into the core. So, we're going to take a
54:3332-bit 16 or 8 bit value and we're going
54:36to put it into a 32-bit register.
54:38>> That's a load. That's a load because
54:39we're from Oh, because ARM ARM doesn't
54:42care about memory. ARM doesn't care
54:44about peripherals. ARM only cares about
54:46the core's point of view. They designed
54:48it that way. So from ARM's point of
54:49view, we're loading into the register.
54:51>> Then the answer would be or I think the
54:54answer might be because
55:01>> Yep. Exactly. There there's no there's
55:04no like type casting or anything weird
55:05in memory. it's just bits and um now
55:09it's your job as the programmer to keep
55:13track of what is the data type you put
55:15in there. Okay, so the value is is
55:17pretty minimal. Then
55:20uh okay, a word of caution with IDE and
55:23I mess this up at least once a year. How
55:26you display information in your IDE
55:28depends on the endingness. Right? So
55:30these are all the same values, but I
55:32asked my IDE to display in 8 bits, 16
55:36bits, and 32 bits, right? And it's using
55:39the same kind of mental model I talked
55:41about before. It's incrementing
55:42addresses by four. In fact, it's
55:44incrementing down in this particular
55:46tool, right? Um, but it's just you can
55:49get easily confused about which which
55:52way is being represented. It gets me
55:54once a semester.
55:57All right.
55:58Now specific for ARM we have special uh
56:03load operations. We have special cases
56:05for load. So we have offset and
56:07pre-indexing and post-indexing. So a
56:09normal load function. So this is
56:11register space inside the core that is a
56:14data space and memory. Okay. And here we
56:17have a a load function which is going to
56:19take the address is stored in R0. Go to
56:23that address and put it into R1. So
56:25we're going to go here. This is a 32-bit
56:27operation. is going to take all those
56:29bits and put them in there. Normal load,
56:31nothing fancy. Then we have offset
56:34indexing which allows us to offset from
56:38this value. And what you're going to
56:39find out this is particularly useful
56:40because how they've organized memory is
56:43that they might have like a GPO
56:45peripheral and they're always going to
56:47store the second bit of any port is
56:50always going to be the same thing or the
56:51third bit or whatever the address is. So
56:53because there's so much uh repetition in
56:56the structures of microcontrollers,
56:58having a base address and then indexing
57:00off of it is a useful uh modality. Also,
57:04if you want to iterate through lists or
57:06uh those sorts of things, uh having a
57:08base address and being able to index is
57:09useful. And so they the compile they you
57:12know they they did workload evaluations
57:14and they say okay this is so so often
57:16used we'll give special instructions
57:18just to support this. So here we're
57:21going to go uh assuming the same thing.
57:23We're going to go the value stored in R0
57:25is the address and then we're going to
57:27store in R1, but as we go we're going to
57:30on the fly add four to it. So we're
57:32going to increment that value and go to
57:34a different set of addresses and we're
57:36going to bring those four in and we're
57:38going to place it in R1. Okay,
57:42so that was uh that's offset indexing.
57:45Now pre-indexing
57:47is uh so here we have we're going to
57:50pre-index by four. It could be a larger
57:52number, right? It doesn't just have to
57:53be four. It could be a negative number.
57:54So we have four and then we have a bang
57:56and and when I think of asking bang as
57:58in immediately right now it's going to
58:00happen. So what it does is it augments
58:02the value stored in the register. So
58:05we're going to uh on the fly oh wait uh
58:08oops did I go wrong? I went the wrong
58:10way. Here we go.
58:12So before we do the memory uh uh the
58:16fetching of the information, we're going
58:18to offset this value. We're going to
58:20make that value four in one instruction.
58:23It's going to update that R0 and then
58:25it's going to go and grab that value and
58:27put it into memory.
58:29>> Yeah.
58:34>> Yes. So this one just offset indexing.
58:37Oops. This never actually hit the
58:39register. This was like on the fly. the
58:41ALU as it's going out trying to find
58:44that uh address this adds four to it
58:47right but here it never changes the
58:50register
58:51in pre-indexing it changes the register
58:55then it goes out and all does it in one
58:57operation okay
59:00and then you have the the inverse of
59:02that postindexing where you go through
59:05and you say okay in post the last
59:07operation after I've gotten the
59:08information I'm going to uh iterate or
59:12imp increase the uh value stored in R0.
59:14So the next time in my loop uh it has
59:17four on it. So it's this is a statement
59:19about compared to the memory access
59:21where does that value get updated and
59:23does it get updated? Yeah.
59:28>> Uh you know is that you're running
59:30through some loop and is it that you did
59:33your operation before the indexing or
59:35after the indexing? It's kind of like an
59:36off by one scenario.
59:38>> Is that does the compiler take your plus
59:41versus plus+ I and do that
59:43>> it could I mean compiler does anything
59:46compiler does wild things but yes that
59:49that is it's I would say it the other
59:51way which is these workloads are so
59:52common that they made special
59:54instructions for this
59:58uh yeah so those are there's four
1:00:01different types there's no indexing
1:00:02there's um pre-indexing without updating
1:00:06there's pre-indexing with updating and
1:00:08there's post updating basically It's
1:00:10just uh does that value get in stored in
1:00:14the register the address value get
1:00:15manipulated and when does it get manip
1:00:17manipulated
1:00:20all right and the interest of time you
1:00:23guys have seen branching functions and I
1:00:25bring these up because there's different
1:00:27types of branching functions there's
1:00:29branch there's branch while updating
1:00:30your link register there's branch with
1:00:33uh indirect updating uh different oh and
1:00:36and uh branching to a particular label
1:00:38or a value in a register. So there's
1:00:41four basic basic different types of uh
1:00:43branching functions.
1:00:45The other trick is that with those ALU
1:00:47flags now you can concatenate them uh to
1:00:50make a whole bunch of different
1:00:51branching conditions. So you can say I'm
1:00:53going to add in branch uh when greater
1:00:56than. And so by concatenating these
1:01:00things together so branch uh greater
1:01:02than and then your label. Now the branch
1:01:06function will go and look to see if
1:01:08those conditions have a meant and then
1:01:10it will switch. Okay, so this is just
1:01:12coming back to the program status
1:01:13register. You you get to use those
1:01:16values. So um if you need to in your
1:01:19function and then you can manually set
1:01:21some of those without necessarily having
1:01:22to do an add or a subtract. There's um
1:01:26uh fun instructions here like compare
1:01:28test that allow you to um you don't need
1:01:32to set the s bit. So, normally for an
1:01:34ad, if you want to update the uh al or
1:01:37the program sash register flags, you'd
1:01:39have to go and put the s here. These
1:01:41don't require that and they don't need a
1:01:42destination register. They just need to
1:01:43know what two things you're going to
1:01:44compare. And all these functions do is
1:01:47update uh those flags.
1:01:51All right, any questions before we go to
1:01:53an example?
1:01:59Not one question, huh?
1:02:01Okay,
1:02:03let's see.
1:02:07All right, so as promised in this class,
1:02:09we will have little worksheets. Get your
1:02:11brains thinking.
1:02:13Uh so you fill them out, you hand them
1:02:16back in at the end of class. Uh
1:02:19there's probably enough over there. You
1:02:20guys can work together. It's not a quiz.
1:02:27Here we go. Maybe one. Oh, here. A for
1:02:30the guy behind you. Can you can I
1:02:32deputize you to go up that row over
1:02:34there and start handing some out?
1:02:38There you go. Let's see. Hand them that
1:02:42way.
1:02:44Let's see.
1:02:47There you go. Oh, you probably need more
1:02:49than that.
1:02:51Yeah,
1:02:54there you go.
1:03:05She needs one over there.
1:03:13>> Yeah.
1:03:15>> Yeah.
1:03:20>> Let's see. You can hand them down.
1:03:24Go. Yep.
1:03:29Go.
1:03:31>> Let's see. I don't know. You look like
1:03:33you're Did they make them down there?
1:03:38>> Okay, we'll get them there. Here you go.
1:03:46Howdy. You go.
1:03:50All right.
1:03:54You got any extras? All right,
1:03:56everybody's got some.
1:03:59Anybody missing one?
1:04:02Oh, okay. Go work together.
1:04:07>> You can write in decimal. I think your
1:04:09brain of uh the value
1:04:31We have over here.
1:05:06Go back to the
1:05:47So I
1:06:13>> [clears throat]
1:06:30>> I want
1:06:46>> [snorts]
1:06:49>> You're going
1:06:52to be [clears throat]
1:07:07Yeah.
1:07:27>> [clears throat]
1:07:54>> Yeah.
1:07:56I
1:07:58am.
1:08:23Hallelujah.
1:08:25Heat. Heat.
1:08:34[laughter]
1:08:49I love you. [snorts]
1:08:57Yeah.
1:09:03Heat.
1:09:13Yeah.
1:09:38>> [clears throat]
1:09:46>> Heat. Heat.
1:09:52Heat. Heat.
1:10:02Heat. Heat.
1:10:20Heat. Heat.
1:10:30Heat. Heat.
1:10:42Heat. Heat.
1:10:52Heat. Heat.
1:11:02Heat. Heat.
1:11:12Heat. Heat.
1:11:22Yeah.
1:11:48Everybody
1:12:01Heat. Heat.
1:12:11Heat. Heat.
1:12:24Hallelujah.
1:12:36Amen.
1:12:56I like
1:13:17>> [clears throat]
1:13:54>> together.
1:14:01That's
1:14:08That's
1:14:12another
1:14:38Okay.
1:14:59Oh my god.
1:15:04Heat. Heat.
1:15:11[snorts]
1:15:22Hallelujah.
1:15:36Heat. Heat.
1:15:49Hallelujah.
1:16:07I'm sorry.
1:16:26Yeah.
1:16:40Heat.
1:16:53All right, let's go through this problem
1:16:55here. I have this little online
1:16:56simulator. If you find it, it doesn't do
1:16:58exactly ARM V7N, just ARM V7. So is the
1:17:02instruction coding is going to be
1:17:03slightly different, but we'll at least
1:17:05for the the purpose of this example,
1:17:07we'll just use this thing. Okay. And so
1:17:10I've got my code over here and I've got
1:17:12memory in set up like yours that hex 98
1:17:16gives a certain value 64.
1:17:19All right. And then we're going to go
1:17:21through. We're going to compile.
1:17:23Great. And let's see what else we have
1:17:26here. We have Do you guys see that?
1:17:29Probably. Maybe. Uh we have our
1:17:31registers over there. So we have R0 at
1:17:33the top going all the way down to PC at
1:17:35the bottom and some other program status
1:17:36registers we don't care about. And now
1:17:38we're going to do the first function.
1:17:40Right? [clears throat] This first
1:17:41function is a move. It's going to move
1:17:43the value of a decimal 152 into the
1:17:49register. Which register? R0. And our
1:17:52dissembler has done a nice job and
1:17:54already told us what the hex value is.
1:17:56So here step into it. You can see that
1:18:00uh the R0 has been incremented. In fact,
1:18:02our PC has been incremented as well.
1:18:04Okay. or our R0 sorry has been loaded
1:18:08with 98. Okay, everybody good so far?
1:18:12Okay, then we're going to go and we're
1:18:14going to do our load function, right?
1:18:16And so load from the core's point of
1:18:18view is going to take the value in R0
1:18:21and store it in memory at the address
1:18:23defined by R0. Sorry, the value in R1
1:18:26and store it in memory at the location
1:18:27R0. And uh the trick that was not clear
1:18:31is that R0 was this 64 or sorry I went
1:18:36too fast we pre-indexed but it just
1:18:38stored it right back into location was
1:18:40already at. So it overwritten wrote that
1:18:42thing and then because this is post
1:18:44indexing after the memory operations
1:18:46happened it's incremented that that
1:18:49pound two there has incremented R0. It
1:18:51was a hex 96 and now it's hex 98.
1:18:56How are we doing?
1:19:00All right, keep going. Now, we're going
1:19:02to get into our loop. We're going to
1:19:03start doing some stores.
1:19:05Uh, we're already doing that. We're
1:19:07going to do our next one. Here is
1:19:08pre-indexing. So, [clears throat] we
1:19:10went through and we stored the value
1:19:12into um that was in R1 into the address
1:19:16defined by R0. However, on the fly, we
1:19:19added two to it. So, now we've
1:19:21incremented a full address space. And we
1:19:23can see that if we do this, let's see.
1:19:26Will it work? Yes, we've uh changed our
1:19:30address over here and we've taken the
1:19:32value in R1 and we put it into 9 C
1:19:37because we added two two times, one at
1:19:39the end of the first store and one at
1:19:42the beginning of the first store. So
1:19:43that the value in R one uh has been
1:19:47stored and it didn't get any offboundary
1:19:50errors or anything.
1:19:54Okay, keep going and we'll do the

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