[CS61C FA20] Lecture 31.4 - I/O: DMA — Transcript

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1. 0:00[Music]
2. 0:10hello
3. 0:11and welcome back to our discussion about
4. 0:14input output so we have seen two
5. 0:16mechanisms
6. 0:17for working with input output devices so
7. 0:20far
8. 0:22we have seen polling of
9. 0:26io devices and interrupts
10. 0:29interrupts are actually being
11. 0:31practically used for the devices that
12. 0:33don't generate a lot of data and don't
13. 0:36consume a lot of data
14. 0:38those that consume a lot of data
15. 0:42are generally nowadays based on
16. 0:46direct memory access so that's a
17. 0:48different mechanism
18. 0:50and let's introduce it here so far
19. 0:54the only device that was able to control
20. 0:57data transfers to the main memory was
21. 1:00the processor itself
22. 1:03in order to offload the processor so it
23. 1:05doesn't spend
24. 1:06a lot of time handling these loads and
25. 1:09stores
26. 1:10we need to come up with a new device
27. 1:13that is new piece of hardware that is
28. 1:15going to
29. 1:16help processor move large chunks of data
30. 1:20to and from the main memory
31. 1:25so that dma engine
32. 1:28is may exist on the same
33. 1:32die as our processor but it will
34. 1:37operate it will take control over the
35. 1:40memory channels
36. 1:42under supervision from the cpu
37. 1:45so essentially what is going to happen
38. 1:47here is the dma engine
39. 1:49will work independently it has
40. 1:52some registers that are written by the
41. 1:55cpu
42. 1:56you know perhaps memory mapped
43. 2:00and these registers are going to contain
44. 2:03the memory addresses to place the data
45. 2:08the number of bytes to be transferred
46. 2:11the number of the i o device that is
47. 2:13supposed to do that
48. 2:14direction of the transfer to the memory
49. 2:17on or from the memory
50. 2:19and the units of transfer and how much
51. 2:24should it do per burst because it can do
52. 2:26multiple
53. 2:27bursts of certain duration
54. 2:31uh per transfer so to illustrate how
55. 2:34does that work here is a picture
56. 2:37from a textbook that we can use so
57. 2:41the cpu is the one that will initiate
58. 2:44the transfer whether it is going to the
59. 2:46memory or from the memory it will write
60. 2:48the address the count and control bits
61. 2:52into the dma controller
62. 2:56in turn the
63. 3:00dma will request transfer to the memory
64. 3:04uh from the device perhaps you know
65. 3:06somebody who
66. 3:07generally is has plenty of data to move
67. 3:10around
68. 3:11is the disk or this controller that may
69. 3:14be controlling multiple disks
70. 3:16so disks modern disks generally have
71. 3:20buffers and
72. 3:21they can read ahead and buffer some
73. 3:24amount of data and non-negligible amount
74. 3:26of data
75. 3:27on them so dma engine is going to
76. 3:30tell it basically to transfer the
77. 3:32contents of its buffer
78. 3:34to a particular location in the memory
79. 3:36that has been specified
80. 3:38by the cpu when it is done
81. 3:43with the transfer it'll sell
82. 3:47this controller will send an
83. 3:48acknowledgement to a dma engine
84. 3:50and dma engine will interrupt the cpu to
85. 3:54tell
86. 3:54that it is done that that file has been
87. 3:57moved
88. 3:58and the transfer has been completed so
89. 4:03the cpu gets interrupted only twice
90. 4:06first
91. 4:07to start the transfer
92. 4:10then the transfer may be long we may be
93. 4:13moving megabytes or gigabytes of
94. 4:15of data which is what i generally do
95. 4:17with
96. 4:18when moving these videos back and forth
97. 4:22and then you know while the data is
98. 4:26moving the cpu can do something else
99. 4:28and then when it's done it gets
100. 4:29interrupted again to
101. 4:31just know that the file
102. 4:35movement has completed
103. 4:38all right let's you know step through
104. 4:41that
105. 4:42for the incoming direction of the data
106. 4:46so the processor will receive
107. 4:49the interrupt from the device uh it
108. 4:52would take the interrupt
109. 4:53and um through a trap handler
110. 4:58it would initiate the transfer it would
111. 5:00instruct the dma
112. 5:02engine to place data at certain
113. 5:05addresses
114. 5:06in the memory the
115. 5:09device and the dma engine are going to
116. 5:11handle the transfer themselves
117. 5:13cpu is free to continue executing a
118. 5:16program it returns from the interrupt
119. 5:18and continues doing whatever it has been
120. 5:19doing
121. 5:20upon completion completion the device
122. 5:23the disk
123. 5:24in this case and the dm engine interrupt
124. 5:28the cpu again
125. 5:29generally the device interrupts
126. 5:32acknowledges to the
127. 5:36dma controller and dma controller
128. 5:38interrupts the
129. 5:40the cpu to tell that is is done
130. 5:44in the outgoing direction of the data if
131. 5:47cpu
132. 5:48has something that would like to move
133. 5:51from
134. 5:52memory to an external device it
135. 5:55initiates the transfer first it confirms
136. 5:58that
137. 5:59the device is ready by reading its
138. 6:03control register and then begins the
139. 6:06transfer
140. 6:08probably more properly we would say here
141. 6:11initiates the transfer it instructs the
142. 6:13dma engine
143. 6:14um to work with the device
144. 6:18that to tell it that the data is
145. 6:20available at a certain address in the
146. 6:22memory
147. 6:23and then um the the
148. 6:26dma is going to work with the device say
149. 6:29a disk
150. 6:30to handle the transfer cpu does whatever
151. 6:33it
152. 6:34wanted to do next and the device
153. 6:38acknowledges that it has received the
154. 6:40data to the dme
155. 6:41dma engine which interrupts the cpu
156. 6:45to signal the completion that is it that
157. 6:48sounds
158. 6:49fairly simple and cool these things did
159. 6:52you know we mentioned that we had
160. 6:55programmed io as
161. 6:56a mode operation say in the 90s
162. 7:00with 88 disks dma has replaced that
163. 7:04in 2000s and most of the disks nowadays
164. 7:07or all of this nowadays
165. 7:09do support dma transfers
166. 7:13but there are some other problems these
167. 7:15dma
168. 7:17controllers that share the the
169. 7:20chip area with the processor we have
170. 7:23freedom where we would like to to to
171. 7:25plug them in
172. 7:27so where do we want to put our dma
173. 7:29controller in the memory hierarchy
174. 7:31well there are two extremes and many
175. 7:33other variants
176. 7:34first we can put it between the cpu and
177. 7:37l1 cache so we can plug it in right
178. 7:40there
179. 7:41[Music]
180. 7:42if we do that we got free coherency
181. 7:45meaning the processor memory system
182. 7:48cache system is going to handle the
183. 7:49coherency
184. 7:53the problem here is that every time we
185. 7:55initiate a dma
186. 7:57may transfer we're going to trash the
187. 7:59cpu's working set
188. 8:01with transfer data the other option is
189. 8:05to put it between the last level cache
190. 8:07and the main memory
191. 8:09so we don't miss processor caches
192. 8:11processor
193. 8:12on the interrupt can just after handling
194. 8:15an interrupt can
195. 8:16resume what it was doing but
196. 8:20the challenge here is that we
197. 8:24need to implement a new coherency engine
198. 8:27and that is usually what is being done
199. 8:30somehow the dma
200. 8:31has to work with a key
201. 8:35with a coherency engine to support it
202. 8:40that's it for the dma and for generally
203. 8:44handling i o devices just one more quick
204. 8:47example is coming up
205. 8:49and then we are done with this module
206. 8:52see you after a quick break