[CS61C FA20] Lecture 22.3 - Pipelining II: Pipelining Datapath — Transcript

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1. 0:01[Music]
2. 0:13hi
3. 0:14welcome back to our pipelining module
4. 0:17previously we have seen how pipelining
5. 0:20is applied
6. 0:21to laundry processing and we have also
7. 0:23outlined
8. 0:24how should we pipeline a risk five data
9. 0:26path
10. 0:28a conclusion there is that if we would
11. 0:30like to build a five-stage pipeline
12. 0:33we should define divide the the
13. 0:35execution into
14. 0:36five stages instruction fetch
15. 0:39instruction decode
16. 0:40execute memory access and write back so
17. 0:43let's
18. 0:44take a look at our single cycle data
19. 0:47path
20. 0:48that we are well familiar with by now
21. 0:50and see how should we pipeline it
22. 0:52so here is our single cycle data path
23. 0:56it has familiar blocks that we have seen
24. 0:58before like the program counter
25. 1:00instruction memory this uh fixed plus
26. 1:03four adder
27. 1:04um immediate generation register file
28. 1:07branch
29. 1:09comparator um alu
30. 1:12and the data memory and multiplexers
31. 1:14that help configure this data path to
32. 1:16execute a particular instruction
33. 1:18and of course there is the control logic
34. 1:20that
35. 1:21configures the data path
36. 1:25we have also outlined that there are
37. 1:28different stages of execution inside
38. 1:30this data path
39. 1:31and those are the stages that we're
40. 1:33going to break down
41. 1:35into different pipeline stages
42. 1:38to recap these stages are the
43. 1:40instruction fetch
44. 1:41instruction decode with register read
45. 1:44alu execute stage memory access and
46. 1:47write back
47. 1:48the instruction fetch starts on the
48. 1:51rising edge of a clock
49. 1:54by incrementing the program counter
50. 1:58and it finishes by having the data read
51. 2:01out of the instruction memory
52. 2:04remember our memory read and
53. 2:07register access are treated as
54. 2:09combinational
55. 2:11logic operations meaning that they do
56. 2:13not rely on clocks
57. 2:15and as soon as the data is stable at the
58. 2:18output we
59. 2:19conclude we assume that that operation
60. 2:22has been concluded
61. 2:23has been finished so as soon as the
62. 2:26instruction
63. 2:26here instruction bits are stable at the
64. 2:29output of the instruction memory
65. 2:30we move on to the next stage the next
66. 2:33stage is instruction decode
67. 2:35when when where will this decode this
68. 2:37memory and
69. 2:38read the registers again the registers
70. 2:40are read
71. 2:41like a combinational logic so as soon as
72. 2:44those values
73. 2:45are stable at the output of the
74. 2:48register file the instruction the code
75. 2:52phase
76. 2:52is done we move on to the
77. 2:55execution phase or the execute phase
78. 2:58where we perform the alu
79. 2:59operation and that one is done when the
80. 3:02output dlu is valid
81. 3:04we move on to the memory access phase
82. 3:07if we are accessing memory in loads or
83. 3:09source
84. 3:10and when we are done with that we move
85. 3:13on
86. 3:13to the right back where we write back
87. 3:16into destination register
88. 3:18in the
89. 3:22register file on the rising edge of a
90. 3:23clock
91. 3:25so how do we pipeline well we simply
92. 3:27insert registers at appropriate places
93. 3:30at the end on the boundary between each
94. 3:33of these execution phases
95. 3:35we need to put registers so we are going
96. 3:38to have registers here that are
97. 3:39conveniently labeled as ifid
98. 3:41id ex exma and mawb
99. 3:47to separate various execution phases
100. 3:54let's take a look at a few of the
101. 3:55highlights here although this looks
102. 3:57fairly
103. 3:58familiar first
104. 4:02at the end of the instruction fetch
105. 4:04phase
106. 4:05we have two registers we have a register
107. 4:09for the program counter
108. 4:10and for the instruction the latter one
109. 4:13is particularly interesting
110. 4:14keep in mind that we have five
111. 4:16instructions in flight
112. 4:18while one of them is being fetched we
113. 4:20have copies of the
114. 4:22previously fetched four instructions
115. 4:24down the stream
116. 4:25so we need to save those instructions
117. 4:27that's why we have them in
118. 4:28this register then in the registers
119. 4:31below that and so on
120. 4:35each one of these pipeline registers
121. 4:38will have to hold
122. 4:39the bits that correspond to the to the
123. 4:42instruction that is being
124. 4:44executed in that particular stage
125. 4:47otherwise we will know what that stage
126. 4:49is doing so that stage has to
127. 4:51keep the instruction but also control
128. 4:54bits that correspond
129. 4:55to that the other thing
130. 4:58that should be noticed here is that um
131. 5:02we are sending down the program counter
132. 5:03and we are pipelining the program
133. 5:05counter
134. 5:06value but we are not sending down the pc
135. 5:09plus 4 value
136. 5:11instead we are recreating pc plus 4
137. 5:15value
138. 5:15in the memory access stage
139. 5:20that's a design decision it is cheaper
140. 5:23to have a
141. 5:24fixed function adder plus four adder
142. 5:26instead
143. 5:27of using one two three
144. 5:30uh registers to store three
145. 5:3332-bit pc plus four values the other
146. 5:36thing that we notice here
147. 5:38we are using the pc value
148. 5:41more upstream here in the first three
149. 5:43stages of execution and then we need
150. 5:45only pc plus 4
151. 5:47down in the memory access stage
152. 5:52to send it down to be written back if
153. 5:54needed
154. 5:57and that is essentially it it looks
155. 6:00fairly
156. 6:01straightforward although there are a few
157. 6:03catches that we are going to see
158. 6:05a bit later
159. 6:13the other thing that i just wanted to
160. 6:15highlight here is
161. 6:17this fact that we actually have five
162. 6:19instructions the three
163. 6:20instructions that are in flight here um
164. 6:23the fifth one is not shown that is in
165. 6:25the right back stage
166. 6:26so the oldest instruction the first the
167. 6:27one that made it the furthest down the
168. 6:29pipe the first one the first one that
169. 6:30went into the pipe
170. 6:32made it the furthest down the pipe is
171. 6:34the one in the memory access stage
172. 6:36which is or then the one that is a
173. 6:39little younger than that one
174. 6:41is slt and then we have uh store word
175. 6:45and the one that is being presently
176. 6:50fetched is load word keep in mind
177. 6:54that we do have to pack everything that
178. 6:56is associated with that instruction into
179. 6:58that pipeline stage
180. 7:00so the instruction that is in the memory
181. 7:03access
182. 7:04will have its copy in the register here
183. 7:06and also
184. 7:08the values that correspond to it in
185. 7:11the the associated registers that
186. 7:14precede that stage and the same thing
187. 7:16here
188. 7:17happens before the
189. 7:21execute stage we have copies of
190. 7:23everything that is needed for that
191. 7:25particular instruction
192. 7:26because we are going to get new values
193. 7:29for
194. 7:30the previous for the next instruction
195. 7:31which is store worked
196. 7:35the other thing to keep in mind besides
197. 7:37the
198. 7:38instruction bits we also need to save
199. 7:42the decoded control bits
200. 7:44remember we have control logic that
201. 7:46tells us what
202. 7:47each stage should be doing how each
203. 7:49stage should be configured
204. 7:51so once when we decode the instruction
205. 7:54we in addition
206. 7:55to our instruction we need to send down
207. 7:57the stream all the control bits that
208. 7:59correspond
209. 8:00to that instruction
210. 8:03so each of these
211. 8:07registers that are storing the prior
212. 8:08encounter are going to be a bit wider
213. 8:10to save the necessary control signals
214. 8:15so for example our memory access
215. 8:18stage register or the register is
216. 8:22sitting between the memory access and
217. 8:23the right back
218. 8:24has to con save the control signals that
219. 8:27correspond
220. 8:28to that final right back um
221. 8:31over there and then um you know between
222. 8:35right back and memory access uh between
223. 8:38the execute and memory access we need to
224. 8:40save the bits that correspond to the
225. 8:42memory access
226. 8:43and the write back stages and so on
227. 8:49that is basically it there are some
228. 8:52things
229. 8:52however that are particular to this
230. 8:56to the situation or have multiple
231. 8:59instructions in flight
232. 9:01and which are called hazards we're going
233. 9:04to take a look at the hazards
234. 9:06next see you then