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[CS61C FA20] Lecture 20.4 - Single-Cycle CPU Control: Control Logic Design — Transcript

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0:01[Music]
0:08hello
0:08and welcome back to our s5 cpu design
0:11module
0:12in the past few segments we walked
0:15through the execution
0:16of several instructions and at moments
0:19that
0:19might have felt repetitive and perhaps
0:22boring
0:23but we wanted to accomplish two purposes
0:26by doing that the first one was to get a
0:30good sense
0:31of how long does it take us to execute
0:34an instruction
0:36and we actually ended up measuring that
0:38that will help us
0:39in the next module but the second
0:42purpose was to get a really
0:44good handle on what is the control logic
0:47supposed to do
0:49that's going to make this segment
0:52much easier to understand and make it
0:55look
0:55fairly straightforward
0:58so let's get into that first let's recap
1:02what do we expect control logic to do
1:04control logic can be viewed essentially
1:06as a lookup table this is a lookup table
1:10with a bunch of rows
1:13and columns rows are the inputs which
1:17would be
1:17the instructions that we would like to
1:19execute
1:21the columns would be the control bits
1:24so each row input is
1:28an instruction that we are running along
1:30with the two more inputs these are the
1:32branch
1:33compare comparison outcomes whether the
1:36operands are equal
1:37or less than remember those are the two
1:39arrows that were also pointing down into
1:40the control logic as the inputs
1:42we need those to figure out how to
1:44select some of the control signals
1:47and then each row has a particular set
1:50of control signals that are set
1:53that it needs to correctly execute so
1:56um our well uh familiar
1:59uh the instructions we are well familiar
2:01with is our ad
2:03the ad has its control word
2:07encoded in the first row so we can view
2:10this
2:10as a word it has a number of bits
2:15about 15 of them
2:19so it simply says what is the control
2:21what are the control bits supposed to be
2:23so we know that pc cell is supposed to
2:26be pointing to the input that will take
2:28the next instruction plus four
2:30immediate select is don't care whether
2:31it's a zero or one
2:33or uh actually this is a a three bit
2:36value for the immediate select so
2:38they can be anything zero zero zero zero
2:40zero one
2:41uh zero one zero and so on and it
2:43doesn't matter to us
2:46um also branch sinus
2:50does not matter either because we are
2:51not executing a branch
2:54but a cell and b cell signals
2:57do matter and they should be taking the
3:00inputs from the registers alu is
3:04a 4-bit control signal because
3:07you can do quite a bit of stuff in this
3:10case we're going to encode it to do the
3:12addition
3:13we're going to set its control bits to
3:16do the
3:17addition and then the memory read write
3:20is going to be set to read
3:21register write enable is going to be one
3:24and finally right back select is a two
3:26bit
3:26control signal that will be set to right
3:30back from the alu
3:33so how do we implement this control
3:35logic this essentially
3:36through table there are two options to
3:38do that one of them is to use a
3:40read-only memory
3:41the other option is to use the control
3:44combinational logic a bunch of
3:46hands and words read-only memory is
3:50like a standard memory that we have seen
3:52before
3:54except that we don't write into it
3:57we just read from it so that's why it's
3:58called red only
4:01we actually write to it at the design
4:03time when we are designing this control
4:06logic we populated with ones and zeros
4:09whatever we
4:10whatever we would like to see in
4:11particular control words
4:14so it's relatively easy to do that and
4:17then we will just
4:18read it by pointing to a particular
4:21control word that you would like to get
4:24out of this
4:25read-only memory
4:29so a designer can keep reprogramming it
4:32while designing it and then we can test
4:34it out by executing a whole bunch of
4:36instructions
4:37it's really really easy it's popular
4:40during prototyping
4:42it is also popular popular when we are
4:44trying to perhaps add an
4:46extension so for example we would like
4:48to add
4:49a compressed part of the instruction set
4:53risk 5 instruction set we have heard
4:54about compressed instructions before
4:56so you would just add that part of the
4:58table
4:59to our rom and then try it out in
5:02practice
5:03when we design real chips
5:07control will be designed as a bunch of
5:09end and ors because that's more compact
5:12and it is faster
5:16but let's actually see what do we need
5:18in order to implement
5:19control logic what kind of inputs do we
5:22need well we need to to have a unique
5:24representation for every single one of
5:26these instructions
5:27and we need those two bits for the
5:30branch outcomes
5:33instructions are 32 bits wide but
5:36the relevant information is stored in
5:38only nine bits so somebody can say that
5:40risk 5i arbitrary to i is
5:43just a 9-bit isa
5:47where are the relevant bits the relevant
5:50bits are
5:51the upper five bits of the opcode
5:54the entire function three field
5:57and that one bit from for
6:01from the function seven field the third
6:03bit of the instruction
6:04that is be used for encoding some of the
6:07add subs
6:08and shifts
6:11so there is just a total of nine of them
6:15five plus three plus one if we are going
6:17to add some instructions like a
6:18compressed instruction we would need to
6:20take
6:20a look also at the last two bits or the
6:23least significant
6:24two bits which one
6:27which are set to be one and one for
6:32rb32i
6:34but for now since we're only dealing
6:37with
6:37arbitrary 2i instructions in order to
6:40decode them
6:41we just need those nine bits from the
6:44instruction
6:46and two additional bits which are the
6:49branch outcomes
6:50so we would point to the rom
6:53with an address that is 18 bits wide
6:57and we are going to read out of that rom
7:00a 15 bit
7:01control word this control world word
7:04will
7:04contain one bit for a pc select three
7:06bits for the immediate select
7:08uh a bit for sineness of a branch a bit
7:12for
7:12a select and b select each alu select
7:16will be
7:16a 4-bit control signal memory read write
7:20is a single
7:21control bit register write enable
7:25is also a single control bit and finally
7:27right-back select
7:28is a 2-bit output how does the
7:31rom actually work inside
7:36it's it looks like a lookup table table
7:38literally
7:40we are going to address this lookup
7:42table
7:43with the same stuff that we have had in
7:45the initial
7:46original initial lookup table um we are
7:49going to have
7:51instructions represented by
7:54their nine bit values plus two
7:58bits that represent the branch outcomes
8:01and then in
8:04each row here will be a corresponding
8:07control word
8:08for those instructions first what we do
8:12we decode the address
8:17um these inputs the the the
8:23the the instruction types are binary
8:26encoded
8:28the output of the address decoded is so
8:30called one hot
8:32only one of these lines is going to
8:35light up we are going to address only
8:37one control word
8:39because that's what makes sense we don't
8:40want to have to control two different
8:42control words that would confuse the
8:44data path
8:44we only produce one control word
8:48for each instruction or in instruction
8:51branch combination
8:53so for example our ad would
8:56point to the first line in this
8:58read-only memory
9:00and
9:04if we are executing an ad this is the
9:07only wire that is going to light up that
9:09is this is the only wire that is going
9:10to be true
9:11all the other ones are going to be zeros
9:14so
9:14the output of this
9:18controller we are going to get a control
9:20word
9:22that only corresponds to an add
9:26all the other ones are zeros
9:32in a way you can view this
9:35as an and or structure
9:38in order to only have one of these
9:41lines enabled this address decoder has
9:44to be
9:45a fairly wide end and then in order to
9:48form the output controller word
9:51it can be just an or that's the simplest
9:53way to implement it
9:54so this is an and or structure
9:58in general there is a lot of redundancy
10:01here with
10:02you know many of these entries are going
10:04to be zeros
10:05so that's the idea of trying to simplify
10:09the the entire control logic into
10:12a smaller numbers number of ands and ors
10:15so in this case let's take an example
10:18what is perhaps the simplest
10:20encoding example that we have in our
10:23instruction set
10:24and that would be whether the branch is
10:27assigned
10:27or not so let's take a look at what
10:30encodes
10:32that we are dealing with a branch these
10:34are the instruction bits
10:35six to two these five instruction bits
10:37are telling us
10:38that it's a branch if the values are one
10:41one one
10:42and one one zero zero zero
10:46and then we need to find out in
10:50the funct 3 field function 3 field what
10:53kind of a branch
10:54it is so
10:59when looking at these the bottom two the
11:01last two
11:02are the unsigned branches vltu
11:06and bgeu what is common for them
11:09the and different for the other
11:12instructions
11:13well you can take a look at this middle
11:14bit instruction three bit
11:17it is true only for those two
11:20so that sets the sinus of a branch
11:23in order to decode this branch we just
11:25need to look at that
11:28middle bit instruction three bit and it
11:30tells us
11:31whether the branch is signed or not so
11:34that control signal
11:35is essentially equal to instruction 13
11:38and the branch because you know this bit
11:40will be true for
11:42other types of instructions in order to
11:48decode the branch right i mean the
11:50branch is encoded
11:52with the
11:57lower bits
12:00so it is i
12:04six and
12:09i5 and
12:13not i4
12:16and not i 3
12:21and not i 2
12:25that is our branch
12:31that tells us that the codes all the
12:33branch instructions
12:35and then to just select
12:38that we are looking for an unsigned
12:40branch we add
12:41that with the instruction bit 13. fairly
12:44simple isn't it
12:46this is a wide
12:506 bit wide and gate
12:54keep in mind that sometimes six bit wide
12:57end gates may not be the most practical
12:59thing to implement
13:00so we'll try to break this down
13:01typically into
13:03a couple of gates that's what
13:06our boolean manipulation is for isn't it
13:11let's design the decode logic for add
13:15so add is just one line
13:18in this in this through table
13:22that has our nine bits you know here is
13:25our add
13:27so what we will do to decode that we are
13:32executing an add well he would just
13:34write down the expression
13:35that it is equal to i3
13:40instruction bit being false
13:43i14 is false i13
13:46is false i12 is false all of them are
13:48zeros
13:49and then we need to end this with an r
13:51type instruction
13:53our type is encoded as
14:00i6 being false i5 being true i4 being
14:04through
14:05i3 being false i2 being
14:10false and that's it we can if we are
14:13adding other
14:14extensions we would have to end this
14:17with
14:17one one in the last bit positions but we
14:20don't have to
14:21for the purpose of our project because
14:24we don't have any other instructions
14:27and that's it we've just finished
14:30all what we need to know about
14:31instruction decoding
14:33and we've done more than that we
14:34actually built
14:37a complete risc-v processor we should
14:39celebrate that
14:40which we'll do after a bit of a break

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