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[CS61C FA20] Lecture 20.2 - Single-Cycle CPU Control: Datapath Control — Transcript

by CS 61C Departmental · 1,858 words · 333 segments · language en · Watch on YouTube

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0:01[Music]
0:10hello welcome back to our cpu design
0:13module
0:14we have designed the data path so it's
0:16time to figure out how to design
0:19the that control unit that we need
0:22it that we need to configure the data
0:25path
0:26so remember our picture of how the the
0:29processor
0:30look and work with the memory we had the
0:33processor
0:34and inside the processor we had two main
0:36units the data path
0:38and the control unit the control unit
0:41is essentially what we have already seen
0:45we just haven't designed it yet this is
0:48the data path a different view of the
0:49data path a detailed view of a data path
0:52and the control unit is primarily the
0:54control logic
0:55that is at the bottom of this picture
0:59inside the data path we have the number
1:01of functional units
1:03like the program counter the fixed adder
1:08instruction memory immediate generation
1:10unit
1:11register file branch comparator
1:14alu data memory and a number of
1:17multiplexers that allowed us to
1:19configure this data path
1:20to execute instructions control unit
1:23was that that was setting up these
1:26multiplexers
1:27and other configuration options inside
1:31the data path
1:31to execute different instructions
1:35so in order to really understand how is
1:38this going to be done
1:40let's take a look at execution of a few
1:42instructions
1:43and see how does the control unit
1:46handle them and simultaneously try to
1:50understand
1:51how does the
1:55how many of these different computations
1:59inside or different actions inside the
2:02processor happen concurrently
2:07so we can do that by revisiting some of
2:10the
2:11those instructions that we have
2:12introduced early on before we
2:14had the complete data path um the idea
2:17now would be to
2:19see how they work with a complete data
2:21path where
2:22everything is in place to execute all
2:24the other instructions
2:26so let's visit one of the early
2:28instructions which was the store
2:30word that's the instruction that takes
2:32the value from the
2:33operand from the register rs 2
2:37and writes it into the memory into a
2:40location that is pointed by the base
2:42address which is in register rs1
2:44and the offset which is the immediate
2:48every instruction in our data path
2:51starts execution on
2:52uh clock tick so on the rising edge of a
2:55clock we are going to write a new value
2:57into the program counter it takes a
3:00little bit of a time
3:02for that to appear at the output of the
3:04program counter
3:05at this wire here um you know and that
3:08time is what we characterize and
3:10clock to output delay
3:14so that clock to output delay after a
3:16clock out to output delay
3:18we get a valid program counter
3:21address um here pointing to the
3:23instruction memory but it is also
3:25ready to be updated and perhaps used
3:28later on
3:29down the the stream in the data path
3:32let's visit what is happening so there
3:34are two things that are happening
3:35concurrently we are fetching an
3:37instruction from the instruction memory
3:38and we are updating the program counter
3:41so as we add this plus four to the
3:44program counter we get a new value at
3:45the input of this multiplexer
3:48but it is not going to propagate through
3:50the multiplexer
3:51until we know what is
3:55the new value of the pc select control
3:58signal
3:59we'll need in order to let it go through
4:02we need to know
4:04what is the the actual instruction that
4:06is being
4:07executed and how does it affect pc
4:10select signal
4:12now concurrently we got our instruction
4:15while we are adding plus four
4:16we got our instruction from the
4:18instruction memory one thing that should
4:19be kept in mind
4:20propagation delays through the
4:22instruction memory and this
4:24fixed another are comparable to each
4:27other
4:29why is that i mean you may be puzzled
4:31with this
4:33we said early on that getting anything
4:35from memory is like
4:36going to sacramento and
4:39addition is not doesn't take us as long
4:42as going to sacramento
4:44um keep in mind that this is a local
4:46copy of
4:48a subset of instructions that we have
4:49brought from the memory such that we
4:51have them handy inside the room
4:53so we can just take a look at them
4:55that's a concept of a cache
4:57that is going to be introduced in the
4:58next module but you
5:00we don't need to know anything about the
5:01cache we just need to know that the
5:03instructions are handy
5:05they're accessible to us and the time
5:08that it takes
5:09us to get them is comparable to the time
5:12to add for to the program counter
5:16so as soon as we get an instruction we
5:18can do
5:19multiple things concurrently with
5:22different data that we got from that
5:24instruction we know
5:26that addresses of
5:29different registers in the register
5:31files are always
5:32in the fixed location so we can go ahead
5:34and get
5:35data from those locations even if we
5:37don't need it if this
5:39instruction is not operating on the
5:42on the registers it doesn't cost us
5:44anything
5:45we can get that data and then toss it
5:48later if we don't need it
5:50but we don't have to wait for the
5:51control to proceed with that
5:53simultaneously we can generate an
5:55immediate we do need to know what kind
5:57of intermediate
5:59we want so this is going to be
6:03gated by the control logic but the third
6:06thing that we are going to do
6:09concurrently is determine which kind of
6:12instruction
6:12it is and what should be the values of
6:15control signals
6:16so the control logic is essentially a
6:19number of logic gates
6:20boolean logic gates that we have already
6:22seen that
6:25takes bits from the instruction
6:28and determines the control signals based
6:31on them
6:32so in this case since this is a store
6:35word instruction
6:36it'll set the pc select value to plus
6:38four
6:39as soon as it does that it will let
6:43pc plus four propagate to the input
6:45program counter but it is not going to
6:46be written into a program counter
6:48until we get to the next clock tick
6:52all the other control signals are set
6:54simultaneously
6:56immediate select this select select to s
6:59type
6:59register write enable
7:02um is uh a zero because we are not
7:06writing anything back into the
7:07register file at the end of a store we
7:10don't care about the branches
7:12b select is select set to be uh
7:16picking an immediate a select is picking
7:19the out
7:19the the rs1 value
7:22lu select is going to do the addition of
7:25the offset
7:26with the base address uh
7:29read write signal is going to be set to
7:31right and right back select is a
7:33don't care so while we were doing that
7:37we are also busy with
7:42getting the data out of the register
7:43file and
7:45generated the immediate it is likely
7:47that immediate generation may take a bit
7:50longer than getting data from the
7:51registers
7:52because it is gated by figuring out
7:55which kind
7:56of an immediate we want but it's still
7:58comparable
7:59so we'll get approximately about the
8:01same time the values of rs1 and rs2
8:04and the immediate and we can proceed
8:06with executing the rest of the
8:07instruction
8:08they're going to propagate through the
8:10multiplexers alu is going to add the two
8:13values
8:14and then we have everything we need to
8:16finish the instruction
8:18uh rs1 plus the offset is pointing to
8:20the appropriate address
8:22in the data memory and the operand
8:25and the value that we would like to
8:27write into it is sitting at
8:29data right port of the data memory
8:35the only thing that we need to finish
8:38this instruction
8:39is to raise the clock
8:43a again so on this clock tick
8:46both the program counter and the data
8:48memory get updated
8:50and we have finished this instruction
8:52and we have actually simultaneously
8:54starting execution the next instruction
8:56let's take a look
8:57at another instruction that we visited
9:00early on
9:01and we are going to do that a little bit
9:03faster this time this is
9:05branch if equal instruction
9:08so it also starts on the clock tick um
9:10multiple things happen
9:12concurrently we increment
9:16the pc to a value please pc plus four
9:20but keep in mind that this is
9:23not going to be ready for writing into
9:25the program counter anytime
9:27soon because that will be about the last
9:30thing
9:31that happens in the branch the branch
9:34does not get completed until we know
9:35whether we are taking it or not
9:39so we are fetching this instruction but
9:41we are also lighting up this spot
9:43showing
9:43that we have a program counter value
9:47sitting in front of the a multiplexer
9:51and this happens with every instruction
9:52we just don't take it
9:55don't proceed with this pc value
9:59unless these are branches or jumps so
10:02concurrently with fetching the register
10:04values
10:05and me you know generating the immediate
10:09um we decode what is this instruction
10:13and set the control bits we can't do
10:16anything with the pc
10:17select until we know the outcome of the
10:19branch
10:20but we can set that immediate is of a
10:22branch type
10:24register right is zero we are not
10:26writing anything back to the registers
10:28this is in branch if equal so sideness
10:32does not matter branch if less than
10:35um we don't care about the outcome of
10:38that so we are not going to take into
10:39the consideration when calculating the
10:41control signals
10:43b select is set to 1 to take the the pc
10:46as the input
10:47a select is set b select is
10:50taking the
10:541 which is the value of the
10:57immediate a select is taking value 1
11:01to take the the program counter
11:05alu select is set to add the
11:10the the the two inputs and
11:13memory is set to read because we are not
11:15writing anything to the memory
11:17and right back select is i don't care
11:19[Music]
11:22so we got everything now by the time
11:24while we are setting that
11:26we can take our operands that we were
11:29fetching
11:30from the memory they're ready and so is
11:32the immediate
11:33and we are ready to proceed
11:36we can figure out what is now the
11:41result of a branch comparison and we got
11:44our
11:44result whether the values are equal or
11:47not
11:48that allows us to set the pc select
11:53to taken or not taken value
11:56but we cannot complete the instruction
11:58until we know
11:59where do we go if the branch is taken so
12:02that we'll we'll figure that out
12:04after the alu completes its
12:07operation its addition and
12:11presents this new value at the input of
12:14the multiplexer
12:17at that point we have both of those
12:19signals valid
12:20one of them that is set by the pc select
12:22propagates into the program
12:24counter and that completes the
12:25instruction although the clock
12:28ticks everywhere the only state that
12:31gets updated
12:32is the value of the program counter so
12:34that is what
12:35wraps up the branch if equal instruction
12:39and that is it we are going to take a
12:42look
12:43at more detailed timing in the next
12:46segment
12:47see you then

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