[CS61C FA20] Lecture 20.1 - Single-Cycle CPU Control: Control and Status Registers — Transcript

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1. 0:01[Music]
2. 0:08hello
3. 0:10welcome back to the module in which we
4. 0:12design a risk pipe cpu
5. 0:14we have made an enormous progress so far
6. 0:16we have designed a data path that can
7. 0:18execute
8. 0:20every single instruction from the rb32i
9. 0:23based instruction set that we need to
10. 0:26run any compiled c program so that's
11. 0:30great
12. 0:30but we are not quite done yet
13. 0:34we need just a few more things
14. 0:38so just to recap how we got to
15. 0:41how we got this far we started fairly
16. 0:44simple
17. 0:45we designed the data product and execute
18. 0:48r-type instructions then we added i type
19. 0:50instructions
20. 0:51then s-types b types u types and j-types
21. 0:54ending up with a data path that is
22. 0:58configurable
23. 0:59and can be configured to execute any
24. 1:01instruction
25. 1:02from our base instruction set for that
26. 1:06we outlined what does the control logic
27. 1:09need to do
28. 1:10but we haven't designed that control
29. 1:12logic yet
30. 1:13that's what we're going to do next but
31. 1:15before then
32. 1:17let's take a look at a few other
33. 1:19components that
34. 1:21pretty much every computer needs to have
35. 1:24one of those components
36. 1:26is a set of so-called
37. 1:29control and status registers or csrs for
38. 1:33short
39. 1:35control and status registers
40. 1:38are separate from our base instruction
41. 1:41set
42. 1:41our base general purpose 32 registers
43. 1:46that we have
44. 1:47in our instruction set architecture
45. 1:52they are close to the processor but not
46. 1:55as
47. 1:55close and close to the execution unit
48. 1:58but not as close as our
49. 2:01general purpose integer registers
50. 2:05they're used for different kinds of
51. 2:06purposes they're used for monitoring
52. 2:11the status and performance and also for
53. 2:13communication
54. 2:14with other devices like peripherals or
55. 2:17other units on the same chip
56. 2:23risk five isa um allows space for
57. 2:26addressing up to 4096 csrs although
58. 2:29in most cases we are not going to have
59. 2:31that many of them
60. 2:33um so what are these csrs what are they
61. 2:36used for
62. 2:37well when we talk about monitoring the
63. 2:39performance we often
64. 2:40care about how well are the
65. 2:43programs executing so in that sense um
66. 2:48csrs
67. 2:50may count the number of cycles that we
68. 2:53have executed
69. 2:54or the number of instructions that have
70. 2:56been retired they can be used for
71. 2:58communication with co-processors like a
72. 3:00floating point unit
73. 3:01or with peripherals things like
74. 3:05printers if you like
75. 3:08and often that communication is done by
76. 3:12placing some kind of a
77. 3:14control word into that register
78. 3:17that the peripheral unit is supposed to
79. 3:19pick up and do something with it
80. 3:21and then when it is done it would put
81. 3:23its status in there
82. 3:25ready or waiting or done
83. 3:28and the processor will know that that
84. 3:31action
85. 3:32has been completed in some cases that
86. 3:35communication is just a single bit
87. 3:37or a flag and that
88. 3:40draws parallels with how we work or at
89. 3:43some point used to work with a
90. 3:44postal service so in
91. 3:48old-fashioned mailboxes somebody would
92. 3:50put
93. 3:51a piece of mail in the mailbox and raise
94. 3:53a flag
95. 3:54and then when the mail carrier comes and
96. 3:56picks up that
97. 3:57piece of mail they will lower the flag
98. 4:00or clear the flag that's why we
99. 4:04that's the reason why we call some of
100. 4:07these single bit
101. 4:09pieces of information in processors as
102. 4:11flags
103. 4:13and we set them and clear them
104. 4:16csrs are in pretty much every processor
105. 4:19that is out there
106. 4:21but they're not part
107. 4:24of the base i say they used to be in the
108. 4:28base isa but they've been taken out
109. 4:30for modularity reasons so there is a
110. 4:33standard extension
111. 4:34that covers these csrs in risk five
112. 4:39so how do the these csr instructions
113. 4:41look like well they share
114. 4:43the well familiar i format
115. 4:46there are two types of csr instructions
116. 4:48ones
117. 4:49that have source register the other ones
118. 4:52that use immediates
119. 4:54so a half of them have a register
120. 4:57operand
121. 4:58the other one have the immediate operand
122. 5:02so similar to i format
123. 5:06we have the upper 12 bits reserved for
124. 5:10addresses instead of the immediate here
125. 5:12the upper 12 bits are used for
126. 5:14for addressing the
127. 5:18csrs control and status registers
128. 5:22so since we have 12 bits over there that
129. 5:24we are using
130. 5:25we can have up to 4096 csrs
131. 5:28then we have a field for the source
132. 5:31register or the immediate
133. 5:33functory field designates which
134. 5:36instruction
135. 5:36are we executing rd is the destination
136. 5:40register
137. 5:41and the opcode
138. 5:45is of a system type shared with some
139. 5:47other instructions
140. 5:49so the way how these csrs work is
141. 5:52they generally work or with the
142. 5:56with our general purpose registers so
143. 5:58what we'll be doing
144. 6:00will be swapping the values in csrs with
145. 6:03the values that are
146. 6:04in our general purpose registers so
147. 6:08general and a good example is a
148. 6:11basic instruction csr read write csr
149. 6:14rw that
150. 6:18copies or take the copies what is in
151. 6:21the csr in a particular csr that you are
152. 6:24addressing
153. 6:25and stores that result in destination
154. 6:27register and at the same time
155. 6:30or concurrently takes the value from the
156. 6:32source register rs1
157. 6:34and copies it to the csr
158. 6:41that is done when the destination
159. 6:44register is any register other than x0
160. 6:46if it is x0
161. 6:48then we are not reading the csr because
162. 6:50we cannot
163. 6:51change the value that is in x0
164. 6:54there are two other variants csr read
165. 6:57and then set or clear those are
166. 7:00basically
167. 7:01setting or clearing the flag
168. 7:04that the csr has been read
169. 7:08then we have the immediate variants
170. 7:10which work exactly the same
171. 7:12except that in the source
172. 7:15field we are not storing the address of
173. 7:18the
174. 7:18source register we are storing the
175. 7:20immediate value and
176. 7:22this immediate value is five bits that
177. 7:24needs to be extended
178. 7:25to write a 32-bit csr
179. 7:29and keep in mind that it is always zero
180. 7:31extended
181. 7:32um it doesn't make sense to sign extend
182. 7:35things that are
183. 7:36just status bits we're not really doing
184. 7:39any arithmetic with them
185. 7:41so as an example of a csr extraction
186. 7:43i've mentioned csr
187. 7:44rw which is the atomic read write csr
188. 7:48we'll see later in the course much
189. 7:50better definition of what
190. 7:51atomic means but in this case it means
191. 7:54that we would like to swap the values
192. 7:56in csrs and integer registers
193. 8:00so in this case csrrw reads the previous
194. 8:03value of the csr
195. 8:05and writes it to integer register rt
196. 8:08and then writes what is in rs1
197. 8:12to the csr doesn't change the value
198. 8:15of the source register
199. 8:19this is a bit trickier to implement
200. 8:22what we will do in our project we'll
201. 8:24implement the pseudo instruction
202. 8:27csr write which only writes
203. 8:30the status control and status register
204. 8:34so its format is csr w
205. 8:38csr rs1 and what it does
206. 8:41it's essentially a short for the csrw
207. 8:44where the destination register is x0 it
208. 8:47just writes
209. 8:48the value from rs1 to the csr
210. 8:53conversely the pseudo instructional csr
211. 8:56wi writes the immediate value
212. 8:59you immediate to the csr and when
213. 9:03implementing this there is not much of a
214. 9:05magic
215. 9:06it's just the block of registers
216. 9:08whatever the number of registers
217. 9:10we need and remember since you would
218. 9:13like to write to them
219. 9:14don't forget clocks and write enable
220. 9:17signals
221. 9:18you don't want to scribble over your
222. 9:20controlling status registers
223. 9:22accidentally that's it
224. 9:26but for controlling status registers
225. 9:29there are a few more instructions in the
226. 9:31base instruction set that we will not
227. 9:33implement in this course but sometimes
228. 9:35they pop up in our assembly code so it's
229. 9:37a good
230. 9:38good idea to know uh what they are so
231. 9:40we're not so surprised when we see them
232. 9:43we have equals and e-brakes
233. 9:46both of them are of i format and share
234. 9:49the same
235. 9:50system up code and equal
236. 9:54makes requests to the supporting
237. 9:56execution environment
238. 9:57namely the operating system
239. 10:00such as system calls which would be
240. 10:02linux
241. 10:04syscalls and then
242. 10:08e-brake is used to transfer the control
243. 10:12to the debugger
244. 10:17that's what we have of those and one
245. 10:19more instruction that we
246. 10:21sometimes may encounter is the fence
247. 10:24much more rarely in this class this is
248. 10:26the one that
249. 10:27separates the memory and
250. 10:30io accesses as viewed by other threads
251. 10:34and processes and that is it
252. 10:38will continue building the control after
253. 10:40a break