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[CS61C FA20] Lecture 19.7 - Single-Cycle CPU Datapath II: Summary — Transcript

by CS 61C Departmental · 343 words · 67 segments · language en · Watch on YouTube

Full transcript

  1. 0:01[Music]
  2. 0:10and welcome back to risk 5 cpu design
  3. 0:13in this little mini module we don't
  4. 0:16really have to do
  5. 0:17anything else except to congratulate
  6. 0:19ourselves
  7. 0:20what do we congratulate ourselves on
  8. 0:22well we have just
  9. 0:23designed a complete data path that can
  10. 0:26execute every single one
  11. 0:28of the rv32i instructions from
  12. 0:32risk five isa that's quite amazing that
  13. 0:36enables us to execute us any c program
  14. 0:40that we can compile into this file
  15. 0:42assembly
  16. 0:43on our custom processor that's quite an
  17. 0:46accomplishment
  18. 0:49so every single one of these
  19. 0:50instructions from the risk 5
  20. 0:53green sheet can be executed there are
  21. 0:55two of them that are left to deal with
  22. 0:56os support but we really don't need them
  23. 0:59for
  24. 1:00compiling programs
  25. 1:04so in a very quick summary we have
  26. 1:06designed a complete data path
  27. 1:08it is capable executing all rx5
  28. 1:11instructions
  29. 1:12in a single cycle each now keep in mind
  30. 1:16that we have designed one version of a
  31. 1:19hardware
  32. 1:20there can be multiple different
  33. 1:22implementations
  34. 1:23of risk 5 data path
  35. 1:27in hours not every single instruction
  36. 1:29was lighting up
  37. 1:30every element in the data path every
  38. 1:33unit in a data path
  39. 1:35but every element or every unit
  40. 1:38was lit up somehow so every single one
  41. 1:40of them had a purpose
  42. 1:42we also have seen that the execution can
  43. 1:45be
  44. 1:46generally separated into separate
  45. 1:49phases of execution so we had
  46. 1:52instruction fetch instruction decode
  47. 1:55with register access execute phase
  48. 1:58memory access phase and write back
  49. 2:02and what we have seen that not every
  50. 2:04single instruction
  51. 2:07is active in every single one of these
  52. 2:08phases
  53. 2:10some of them may be active in just four
  54. 2:12out of five phases
  55. 2:15now important thing that we have been
  56. 2:18touching
  57. 2:19on is the this controller that was
  58. 2:22configuring the data path
  59. 2:23to execute the instructions properly
  60. 2:27we have talked about what kind of
  61. 2:28signals we would like to get out of that
  62. 2:30control unit
  63. 2:31but we haven't spent much time or any
  64. 2:35time
  65. 2:35on designing the control unit so
  66. 2:39that's what we're going to do next see
  67. 2:41you then

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