[CS61C FA20] Lecture 19.4 - Single-Cycle CPU Datapath II: Adding JALR to Datapath — Transcript

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1. 0:01[Music]
2. 0:08hi
3. 0:08welcome back to risk 5 cpu design so far
4. 0:12we have built
5. 0:13the data path and the associated control
6. 0:15that
7. 0:16supports r type i type as type and b
8. 0:20type instructions in that process we
9. 0:24have added
10. 0:25pretty much all of the hardware that we
11. 0:27need to support
12. 0:29all of the remaining instructions in the
13. 0:31instruction set
14. 0:32the changes that we need to add that we
15. 0:36need to make to support the remaining
16. 0:37instructions are relatively small
17. 0:39so let's see what do we need to add to
18. 0:41support
19. 0:42gel r instruction that's the instruction
20. 0:44that stands for jump and link register
21. 0:47which is the one that we frequently use
22. 0:50for
23. 0:50function calls
24. 0:54so gel r is an instruction of an
25. 0:57i format that's the same format as we
26. 1:00have used for
27. 1:02arithmetic with immediates and for loads
28. 1:06in that format we have an immediate in
29. 1:09the upper 12 bits and then fields for
30. 1:12one source register
31. 1:13and one destination register so the
32. 1:15format of the instruction is
33. 1:17gel r rd rs immediate the instruction
34. 1:20does two changes to the state
35. 1:23it runs pc plus 4
36. 1:26to the destination register which we'll
37. 1:28be using as the return
38. 1:30address from our function call and then
39. 1:34jumps to the function by
40. 1:38writing the rs1 value
41. 1:41plus the immediate to the program
42. 1:43counter
43. 1:45notice that the use of the immediate
44. 1:49format for
45. 1:52r presented a compromise
46. 1:57we lost one bit of a range because
47. 2:00always the last bit of the immediate is
48. 2:01set to zero so
49. 2:02so we lose one bit of how far we can go
50. 2:05with the gel
51. 2:06r but it simplified the data path we are
52. 2:09essentially reusing the the immediate
53. 2:13generation
54. 2:14mechanism from the i types
55. 2:18so here is the data path that we have
56. 2:21built so far
57. 2:23it has the instruction the program
58. 2:25counter the instruction memory
59. 2:28the register file a branch comparator
60. 2:31that we don't need
61. 2:32this time the alu the data memory which
62. 2:36we don't need either
63. 2:38and the control
64. 2:42we need to do two things first we need
65. 2:44to figure out how to
66. 2:46write the value of pc plus 4
67. 2:49into the destination register in the
68. 2:52register file
69. 2:53and there is no immediate path we'll
70. 2:55need to somehow add a multiplexer
71. 2:57for that to happen then for the second
72. 3:00part where we are going to be adding rs1
73. 3:02within with an immediate we already have
74. 3:04the mechanism we'll be using the alu
75. 3:07and we are going to write it through the
76. 3:09same hardware that we've used for
77. 3:11supporting taken branches
78. 3:14so here is what is the modification that
79. 3:17is needed
80. 3:18to support child r it is just adding
81. 3:21this path
82. 3:24that enables us to write pc plus 4
83. 3:28to the destination register we have done
84. 3:29that by widening
85. 3:32the right back select multiplexer to
86. 3:34have three possible
87. 3:36inputs one or the
88. 3:39right back value may be coming from the
89. 3:41destination memory
90. 3:43one where the right back would be coming
91. 3:46from the alu and the third one
92. 3:48is the pc plus four value
93. 3:51we could have done this differently we
94. 3:52have added one more multiplexer in
95. 3:54series
96. 3:55and another control signal but this way
97. 3:57it's simpler we just widen the
98. 3:58multiplexer and we are using
99. 4:00a three position switch here for right
100. 4:03back select
101. 4:04so right back select has three different
102. 4:06values zero one and two
103. 4:09the rest of the modification is simply
104. 4:12done through the control so there are no
105. 4:13modifications to the data path we just
106. 4:15have to set the control bits the right
107. 4:17way
108. 4:19notable thing here is pc cell control
109. 4:22signal is always set to taken
110. 4:25which means we are behaving like
111. 4:28we are always taking a branch because it
112. 4:31is a jump
113. 4:33um immediate select is of i type because
114. 4:35we are sharing the format with i types
115. 4:38we do enable writing to the register
116. 4:41file
117. 4:42because we do have to write the
118. 4:44destination value
119. 4:46to the destination but we need to write
120. 4:48the return address to the destination
121. 4:50register
122. 4:50we ignore everything it is associated
123. 4:52with the branches we set the
124. 4:54a b multiplexers appropriately and
125. 4:57alu is set for an addition we are not
126. 5:00working with the memory so
127. 5:01we set it to read which is the default
128. 5:03state and right back select this two as
129. 5:05we already mentioned let's light up the
130. 5:08gel r data path we start with fetching
131. 5:11the instruction
132. 5:12and we can immediately proceed to the
133. 5:15decode
134. 5:16one notable thing here is we instead of
135. 5:19lighting up this path of
136. 5:22pc plus 4 value going back to the input
137. 5:24of the program counter
138. 5:26it that does happen but this is a path
139. 5:28that is never going to be taken so we
140. 5:30are just
141. 5:30lighting up the path that takes it to
142. 5:33the right back select
143. 5:35after the control logic sets all these
144. 5:38signals appropriately
145. 5:40we can proceed with the rest so
146. 5:44actually concurrently with setting up
147. 5:46the control registers
148. 5:47immediate generation is going to happen
149. 5:49and rs1 value is going to be
150. 5:52sent over to the alu rs2
151. 5:55is being ignored because it is invalid
152. 5:58we don't have rs2 in the field
153. 6:01in the instruction field the output of
154. 6:03an alu
155. 6:05will be the sum of the rs1 value
156. 6:08with the immediate and that is going to
157. 6:11be
158. 6:12sent back to the pc cell multiplexer
159. 6:14that one is set
160. 6:15always to take that value not the pc
161. 6:18plus 4
162. 6:19that's going to be put at the input
163. 6:22of the program counter so
164. 6:27that is going to happen simultaneously
165. 6:29with the write back select multiplexer
166. 6:31presenting the pc plus 4 at the input
167. 6:35of the rd on the next clock tick
168. 6:39those two states are going to be updated
169. 6:42and that's it we'll see some other
170. 6:44instructions after we come back