[CS61C FA20] Lecture 19.2 - Single-Cycle CPU Datapath II: Datapath for Stores — Transcript

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1. 0:01[Music]
2. 0:09hello
3. 0:10welcome back to this 5 cpu design we've
4. 0:12designed a data pod that we can share
5. 0:14between all r type and i type
6. 0:18instructions
7. 0:18including the loads to support the loads
8. 0:22we have added the memory to our data
9. 0:25path
10. 0:25we access the memory by pointing the
11. 0:30the address to it and then we read the
12. 0:33value
13. 0:34and store it into the destination
14. 0:37register
15. 0:38let's see what do we need to modify in
16. 0:40order to support stores
17. 0:42so here is a representative store
18. 0:45instruction which is store
19. 0:46word in risk five it
20. 0:49reads two registers rs1 and rs2
21. 0:53and the immediate from the
22. 0:56instruction we take
23. 0:59that immediate value we extend it
24. 1:03and add it to the value that is stored
25. 1:05in the registers
26. 1:06register rs1 that is what forms the
27. 1:09address
28. 1:10that is used to access the memory now
29. 1:13when we have that address
30. 1:14we take the contents of a register rs2
31. 1:17and write it to the memory so what we
32. 1:20can see
33. 1:21from this is that we can reuse
34. 1:25much of the data path we are still going
35. 1:27to use the alu
36. 1:28to form the address to add the
37. 1:31immediate value to
38. 1:35the contents of a register rs1 we do
39. 1:38need to
40. 1:39provide an additional path that would
41. 1:42put the contents of register rs2
42. 1:47in the port of the memory that is going
43. 1:50to be
44. 1:50used for writing and we need to modify
45. 1:53the memory to
46. 1:54enable it for writing such that it will
47. 1:56be updated on the next
48. 1:58clock cycle another important thing here
49. 2:01is we need a different
50. 2:02immediate this time so our immediate
51. 2:05generation unit will need to be updated
52. 2:07to be able to support two types of
53. 2:09immediates
54. 2:11in the i type of intermediate our
55. 2:12immediate was
56. 2:14located in the the the top
57. 2:1812 top 12 most significant bits of the
58. 2:21instruction
59. 2:22but in the s format
60. 2:26the immediate is split into two parts we
61. 2:28have still the top
62. 2:30seven bits in the top
63. 2:33twelve most significant top 7 most
64. 2:36significant bits
65. 2:37of the instruction but the lower
66. 2:405 bits are now in locations
67. 2:4511 to 7.
68. 2:48remember this was done such that we keep
69. 2:50the
70. 2:52the the fields that store the addresses
71. 2:54of the registers the same
72. 2:56across all instruction formats because
73. 2:58those are in the critical path
74. 3:00um you would have you can just imagine
75. 3:02now we know the result
76. 3:03the reason for that it would be a mess
77. 3:06to try to move these addresses all over
78. 3:09the place
79. 3:10before we start address accessing the
80. 3:13register file
81. 3:14and raise the file is often in the
82. 3:16critical path
83. 3:19so we'll need a modification to the
84. 3:21immediate generation unit but let's see
85. 3:23what we got so far so what we have so
86. 3:26far
87. 3:26is the data path that supports the
88. 3:30loads and in the loads
89. 3:33i'm just showing the data path with lw
90. 3:37load bytes and load half words need an
91. 3:39additional multiplexer
92. 3:40over here and a few logic gates but i'm
93. 3:43leaving them out
94. 3:44to avoid too much complexity here
95. 3:48so what we had is the data memory we
96. 3:51have added the data memory
97. 3:53that we're going to use to read
98. 3:56the the value from and store it back
99. 3:59into the
100. 4:00register file our alu
101. 4:03points to the address where we would
102. 4:05like to read from
103. 4:07and it is formed by adding the immediate
104. 4:11to the source register rs1
105. 4:14the things that we need we we added were
106. 4:18these control signals at the end
107. 4:21uh mem rw and right back select
108. 4:26let's see what we need to do to support
109. 4:29stores
110. 4:30so in order to support source we need to
111. 4:33modify
112. 4:34our model of the memory such that we can
113. 4:37write to it so two things will happen
114. 4:40our control signal mem read write
115. 4:44is going to be given a value right so we
116. 4:47can write to the memory
117. 4:48on the next clock tick
118. 4:51and we are adding another port to the
119. 4:55memory which is data w
120. 4:57this is where we are going to place the
121. 4:59data that you would like to write into
122. 5:00the memory at
123. 5:02and we are going to ignore
124. 5:05whatever is being read
125. 5:09out of the memory accidentally we don't
126. 5:11care about
127. 5:12anything that appears at the data read
128. 5:14port
129. 5:16so we are setting the right back so
130. 5:18let's select signal to
131. 5:20a star or a donkey we'll use it in logic
132. 5:23optimization later
133. 5:24to minimize the number of gates that we
134. 5:26need in the control
135. 5:29so our data path now is very similar to
136. 5:32what we have seen
137. 5:33in the loads with a few exceptions
138. 5:37immediate select is going to select a
139. 5:39new type of an immediate
140. 5:40which is the s type we are not
141. 5:44writing back to the register file so we
142. 5:46are going to
143. 5:48set the reg right enable signal to zero
144. 5:53and then uh we are still going to select
145. 5:55the b
146. 5:56operand here which will pick the
147. 6:00b operand to be the immediate alu is
148. 6:03still going to
149. 6:04add that immediate to the rs1
150. 6:08and that's how we got our address
151. 6:11let's light up this data path to see how
152. 6:13things actually
153. 6:14propagate through it we're going to cut
154. 6:17through the chase
155. 6:18and we are going to go through the
156. 6:20instruction fetch and
157. 6:21end up with a data with the the
158. 6:24instruction that is going to be decoded
159. 6:27our control logic is now going to
160. 6:29process that instruction and set
161. 6:31appropriate signals in the control such
162. 6:33that we
163. 6:34light up the the right par parts of the
164. 6:37data path
165. 6:38so immediate select is going to be set
166. 6:40to s register
167. 6:42file writing is going to be disabled
168. 6:45b select is going to be set to pick the
169. 6:48immediate
170. 6:50alu is going to be set to execute an
171. 6:52addition
172. 6:54and memory is going to be enabled for
173. 6:56writing the final select signal
174. 6:58is right back is a donkey
175. 7:02so while the control is being lit up
176. 7:06simultaneously we are accessing the
177. 7:08registers and
178. 7:09generating the immediate and what we see
179. 7:11here we got
180. 7:13our rs1 contents in rs2 contents
181. 7:16and the important thing that we see here
182. 7:19is that rs2 although it shows up at this
183. 7:22multiplexer multiplexer is not selected
184. 7:24to take it
185. 7:25rs2 goes around it and goes to the
186. 7:29data port of the memory at the same time
187. 7:32our immediate is formed and goes to the
188. 7:35alu output of that alu
189. 7:37points to the address where we are going
190. 7:39to write
191. 7:40this data and that is it that completes
192. 7:45the store cycle on the next clock tick
193. 7:49the new datum is going to be written
194. 7:51into the data memory
195. 7:52and the program counter is going to be
196. 7:56updated
197. 7:59let's see a little bit about what do we
198. 8:01need to do
199. 8:02to our immediate generation unit our
200. 8:04immediate generation unit
201. 8:06so far was very simple it was designed
202. 8:10to take 12 bits
203. 8:11of the i type from the i type
204. 8:13instruction
205. 8:14and sign extend it to 32 bits
206. 8:19now we have to support both i and s-type
207. 8:22immediates
208. 8:24these immediates
209. 8:27are similar they have the top seven bits
210. 8:31being the same so whatever we have in
211. 8:34the top seven bits in both of
212. 8:36i type ns type instructions is going to
213. 8:38go into the same spot
214. 8:40bits 7 to 12 or
215. 8:436 to 11
216. 8:46of the new immediate with 11th
217. 8:50bit extended all the way to
218. 8:5331st bit for sign extension
219. 8:56but the lower five bits in case of
220. 9:00i type are going to come from the
221. 9:02instruction bits 24 to 20
222. 9:04in in case of s type are going to come
223. 9:07from
224. 9:08instruction bits 11 to 7. so all what we
225. 9:11need to do is to implement one
226. 9:13multiplexer that is going to be working
227. 9:15two way in case of an
228. 9:17i type of an instruction is going to
229. 9:18take bits 24 to 20
230. 9:21in case of s type instruction is going
231. 9:23to take bits 11 to 7
232. 9:25and that's it that logic design is
233. 9:28fairly simple
234. 9:29all what we have is the same logic that
235. 9:31we have had for
236. 9:32i immediate creation and we are just
237. 9:35adding
238. 9:36one multiplexer in front of it
239. 9:39that's most of it that we need to
240. 9:41implement source
241. 9:42there are two other store instructions
242. 9:44in rs5 isa
243. 9:46store bytes and store half words
244. 9:49are um relatively
245. 9:52straightforward to implement we use
246. 9:54exactly the same data path
247. 9:56the only modification that we need to do
248. 9:58with just the gate or two is to make
249. 10:00sure that we don't accidentally override
250. 10:02something in the memory that we should
251. 10:04not
252. 10:05write into that completes the story
253. 10:07about the stores
254. 10:08where when we come back we're going to
255. 10:11add
256. 10:12a few major magnifications to the data
257. 10:14path but that will be it
258. 10:17pretty much everything we need to know
259. 10:20about the
260. 10:20data path see you then