[CS61C FA20] Lecture 19.1 - Single-Cycle CPU Datapath II: Supporting Loads — Transcript

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1. 0:01[Music]
2. 0:10hi
3. 0:10welcome back to our design of risk 5
4. 0:13processor
5. 0:14we've designed a data path that can
6. 0:17execute both r type and i type
7. 0:20instructions
8. 0:22so let's recap it before we
9. 0:25figure out how what do we need to do to
10. 0:27it to add loads
11. 0:31in the data path that we had so far we
12. 0:34had
13. 0:35only four phases of execution remember
14. 0:38we said
15. 0:39typically instruction execution has five
16. 0:42phases
17. 0:42but neither are types or i types that we
18. 0:46have seen so far
19. 0:47did not need to access memory saw
20. 0:51so that phase was dropped first we have
21. 0:54our instruction address stored in the
22. 0:57program counter primary counter points
23. 0:59to the instruction memory and fetches
24. 1:02the instruction that you would like to
25. 1:03execute
26. 1:05in the second phase we could decode that
27. 1:07instruction
28. 1:08and by using the information that we
29. 1:11decoded from the instructions fields
30. 1:13we set the control bits
31. 1:17at the same time we fetch the datum from
32. 1:20the registers
33. 1:22data from the registers and prepare the
34. 1:24immediate
35. 1:26in the third phase we execute the
36. 1:28instruction in the lu
37. 1:30we perform addition subtraction or any
38. 1:33of the logic
39. 1:34operations that we would like to do
40. 1:38based on the instruction fields there is
41. 1:41no
42. 1:42memory access phase in instructions that
43. 1:45we have seen so far so we proceed
44. 1:47straight to the
45. 1:48fifth stage of execution that
46. 1:52is writing back the output of the alu
47. 1:56into the destination register
48. 2:00now in order to support loads and stores
49. 2:02will have to have the data memory
50. 2:05and keep in mind that risk 5 is so
51. 2:08called a load store
52. 2:10type of an architecture where all
53. 2:12operations
54. 2:13with the memory are done just with loads
55. 2:16and stores
56. 2:17no other instruction type accesses
57. 2:20memory
58. 2:21so let's review first what is what do we
59. 2:24need to do with our loads
60. 2:26here is a load word memory that we have
61. 2:28seen before
62. 2:29it is of an i type as well because it
63. 2:32has the same format of
64. 2:34an immediate as the previous i type
65. 2:37instructions that we have seen before
66. 2:39so immediate is 12 bits wide
67. 2:43and it should be signed extended before
68. 2:45it contents
69. 2:46is added to the value in the register
70. 2:49rs1
71. 2:50now that sum of the immediate
72. 2:54and the value from rs1
73. 2:57should not be written straight back into
74. 3:00the destination
75. 3:01register which is what we did in i types
76. 3:05instead it is being used to point to the
77. 3:08memory
78. 3:08address where we would like to retrieve
79. 3:11data from
80. 3:12and then that data that we get from the
81. 3:14memory will be written back
82. 3:16into the destination register so what
83. 3:19does our data path need to support
84. 3:22the first part looks exactly the same as
85. 3:24what we have seen
86. 3:26already in i types shared with r types
87. 3:30except that we need to have memory back
88. 3:33in the picture so memory is right here
89. 3:37and it shouldn't be a surprise we
90. 3:40point to an address in the memory where
91. 3:43we would like
92. 3:44to read the data from and the data
93. 3:47appears
94. 3:48at data r port
95. 3:51we'll take that value from the data our
96. 3:54port
97. 3:54and write it back into the destination
98. 3:57register
99. 3:58but keep in mind we are not building a
100. 4:00separate data path
101. 4:02for loads this is the shared data path
102. 4:05that we had before
103. 4:07so in order to support both arithmetic
104. 4:10instructions
105. 4:11and loads we use a multiplexer and we
106. 4:13select
107. 4:14where does our destination
108. 4:17for right back where does our operand
109. 4:20for
110. 4:21right back come from whether it comes
111. 4:24straight from the alu
112. 4:26or comes from the memory so we have a
113. 4:29new
114. 4:30select signal right back select
115. 4:34in this case memory is configured for
116. 4:36reading so we
117. 4:37you know we treat it essentially as a
118. 4:40combinational block we
119. 4:41don't really care about the clock and
120. 4:44our memory read write is going to be set
121. 4:47to read
122. 4:49let's light up this data path to see
123. 4:52what it actually does
124. 4:55so remember first we have our
125. 4:58next instruction or current instruction
126. 5:00to be executed
127. 5:02in the program counter the program
128. 5:04counter points
129. 5:06to the address in the
130. 5:09instruction memory where the instruction
131. 5:11is
132. 5:12we retrieve that instruction and decode
133. 5:15it
134. 5:16in the second phase of execution when
135. 5:18decoding
136. 5:19that address we find out
137. 5:23when decoding the instruction i'm sorry
138. 5:26we find out what do we want to do
139. 5:28and set the appropriate control to
140. 5:31execute it
141. 5:32so we in this case we'll set the
142. 5:35immediate to be of an
143. 5:37i type we'll see we have other
144. 5:39immediates later on
145. 5:41then we will say that we will write we
146. 5:43would like to write back
147. 5:45into the register file we
148. 5:49pick the b operand in the alu to
149. 5:52be the immediate not the output of the
150. 5:56register rs2 we
151. 5:59set the type of alu operation that we
152. 6:02would like to do
153. 6:03remember we are using alu here to add
154. 6:06the immediate
155. 6:07to the value in rs1 we set
156. 6:10memory read write to read and we set the
157. 6:14write back select
158. 6:15to zero to write back from the memory
159. 6:20in the same phase of execution we
160. 6:23prepare the alu operands
161. 6:26which will be rs1 by reading the
162. 6:29accessing the date the registers in the
163. 6:31register file
164. 6:32and extending the immediate value
165. 6:36in the third phase of execution we
166. 6:38perform the addition
167. 6:41and point to the address in the data
168. 6:44memory
169. 6:45in the fourth phase of execution we
170. 6:47perform the memory access
171. 6:49and finally in the fifth phase of
172. 6:50execution we write
173. 6:52back to the destination register
174. 6:57and that's it this is our support for
175. 7:00the loads
176. 7:01one thing that just has to be kept in
177. 7:03mind there are
178. 7:05several different load instructions in
179. 7:08the risc-5 base
180. 7:11rb32
181. 7:15instruction set um so we have narrower
182. 7:18loads
183. 7:19these narrower loads can load bytes or
184. 7:21half words meaning
185. 7:23they can load eight bit
186. 7:26wide data or 16-bit y data and it can be
187. 7:30of signed or unsigned type
188. 7:33it is supported by the same data path
189. 7:35except that we
190. 7:36may have to add or we definitely have to
191. 7:39add
192. 7:40a few logic gates and a few multiplexers
193. 7:43to support that this is a good exercise
194. 7:46in
195. 7:48logic design and i strongly encourage
196. 7:50you to
197. 7:51take a look at that
198. 7:54you may actually need this for a project
199. 7:56and you will find it in some of the
200. 7:58previous
201. 7:59exams we can break now
202. 8:02before we get to the stores so see you
203. 8:05when
204. 8:05we get to this stores module