YT YouTube2Text

YouTube2Text → Transcripts → [CS61C FA20] Lecture 18.3 - Single-Cycle CPU Datapath I: R-Type Add Datapath

[CS61C FA20] Lecture 18.3 - Single-Cycle CPU Datapath I: R-Type Add Datapath — Transcript

by CS 61C Departmental · 1,715 words · 299 segments · language en · Watch on YouTube

Open in transcriber Summarize with AI Download SRT/VTT

Full transcript

0:01[Music]
0:11hi
0:12welcome back to design number x5 cpu
0:16we said that the cpu can be viewed as a
0:19complex state machine that consists of a
0:21data path and the control
0:22that are shared among all instructions
0:26but we're not going to go and go ahead
0:29and
0:29design the entire data path that is
0:31shared
0:32across all instructions um we
0:35let's try to start with something
0:37smaller so let's design a data path
0:39support one instruction type and in
0:41order to start fairly simple
0:43let's just pick one instruction let that
0:45be the r
0:47type add instruction remember our r
0:50type instructions those were all they
0:52all look similar and those were
0:54registered to register arithmetic and
0:56logic instructions
0:58they would operate on the contents of
1:00two source registers
1:02and store the result of that operation
1:05in the destination register rd
1:07they look similar they had the same
1:09opcode
1:100 1 1 0 0 1 1
1:14and same fields for the destination
1:16register
1:18first source register and the second
1:19source register and they differ by the
1:21encoding of the funct 3 field
1:23and this slight difference in the
1:2630th bit of instruction some of those
1:30were zero some of those
1:31were once so add rd
1:34rs1 rs2 instruction will take the values
1:36in the register rs1 and rs2
1:39and store the result in the register rd
1:43sub rd rs1 rs2 instruction
1:48would subtract the value of register rs2
1:52from the
1:52value of the register rs1 and store the
1:54result in the destination register
1:57rd to take a look a bit in more detail
2:00here is there is no new information at
2:03the top of the slide it
2:04just repeats the encoding for
2:06convenience
2:08but it helps us here illustrate what is
2:10the
2:12change in state of this state machine
2:16that executes instructions so
2:18instruction makes two changes to the
2:20machine state
2:22it updates the content of contents of a
2:26register rd
2:27with the sum of the values of rs1 and
2:30rs2
2:30without changing rs1 and rs2 and it
2:33updates the program counter to a new
2:35value
2:36that is four bytes larger so
2:39we need to build a data path that is
2:41going to do these two state updates
2:44so what we will see first we have a
2:46program counter
2:47that has its own state at the output of
2:51that program counter
2:52there is a current value of pc
2:58that points to the address in the
3:01instruction memory
3:03by pointing to a particular instruction
3:06in the
3:06instruction memory we'll read its
3:08contents
3:10and that will be an instruction that we
3:12would like to execute remember
3:14our model for the instruction memory is
3:15fairly simple we just need to point
3:18and the instruction is going to show up
3:20at the output we don't need the clock
3:22simultaneously we need this piece of a
3:25hardware we need this fixed function
3:27adder that will be always adding a value
3:294 to the current value of the pc and
3:33putting will be put pc plus 4 value at
3:37the input of the program counter
3:39now remember the contents of the
3:43program counter will not change until
3:45the next
3:46clock tick on the next rising edge of a
3:50clock
3:51program counter will take a new value of
3:54bc plus 4.
3:55but let's see what else do we need to do
3:58with this instruction
3:59so decoding instructions is
4:02fairly straightforward because we are
4:05going to always find
4:07things in the same place so our
4:09instruction
4:10here needs to point
4:14to the register file and conveniently
4:17we always are pointing to the same
4:19places in the register file we know that
4:21if we take
4:22a part of that instruction that
4:26contains bits 19 to 15
4:30will point to the address of rs1 so all
4:34what we need to do
4:35take those five bits from the
4:37instruction and connect them to the
4:39address port
4:40the first address port of the register
4:42file remember we are using
4:45a register file that simultaneously can
4:47read two
4:48registers so we're going to take the
4:50second
4:52collection of bits 24 to 20 and
4:55hook them up to the address of the
4:57second port
4:58as a result this register file
5:01will produce the outputs that correspond
5:06to the contents of a register rs 1 and
5:09rs2
5:10then all what we need to do is to add
5:11them together by using our alu
5:14alu is configured to be very simple here
5:16to just do addition so this is just an
5:18adder
5:19we'll get the new value at the output of
5:21an aldu
5:22that needs to be written into the
5:24register file to where does it should
5:26be written to the register rd where it's
5:29register rd we know from the instruction
5:31it is
5:33at the address that instruction bits 11
5:36to 7.2
5:37so on the next clock tick we are going
5:40to write that
5:41in to our destination register rd
5:46what else do we need to complete this
5:49well
5:49let's recap first what what we need to
5:52to do to
5:53to execute the whole instruction first
5:56we
5:59have the the current value of the
6:03program counter
6:04points to the address in the instruction
6:07memory
6:08that is going to after and the access
6:10delay
6:11produce the instruction its output
6:13simultaneously we are going to get a new
6:15value of the program counter pc plus 4
6:17but we are not going to write it in
6:19until the next
6:20clock tick now let's take a look at what
6:23is happening with the instruction itself
6:26decoding is straightforward we just
6:28pluck the parts of that instruction
6:30point
6:31to the register file notice that we
6:34already have the
6:35the address of the destination register
6:37so it will just show up at the input
6:40of the register file although it we are
6:42not going to do anything with it
6:44our results are going to show up at the
6:46output of the register file
6:48after the alu delay we are going to get
6:51the new value that should be written in
6:53the rd and it is just
6:54going to be sitting at the input of the
6:57register file until the
6:58next clock tick then two new values pc
7:02equals to pc plus four and rd equals to
7:05are the values of of rs1 and rs2
7:09is going to be updated on the next clock
7:12tick
7:13what do we need to complete this we need
7:15control and in this case control is
7:17fairly simple because
7:18we have a fixed function value that just
7:20does the addition so all what we need
7:22to do is to enable register file for
7:25writing to so we need to have this
7:29control register that enables
7:32writing into into the register file
7:36asserted the signal regret enable
7:39has to be equal to one let's take a look
7:41a bit at the timing
7:42of addition so here is the repeated data
7:46path it's exactly the same as what we
7:48have had in the previous
7:50slide we just added explicitly clock
7:53to see how does it orchestrates the
7:55operation of the cpu
7:59let's see what is happening as time goes
8:01by and time is going to move here
8:03from left to right
8:07we are going to look at what happens at
8:10roughly three clock
8:11cycles during three rising edges of a
8:14clock and we're actually going to focus
8:16only on two of them
8:17first on the first clock tick we update
8:20the value of the program counter and we
8:22write a new address into the program
8:24counter
8:25in this case it is one zero zero zero
8:28okay uh we're using some short kind of a
8:31short handle notation here yes because
8:33the program counter
8:34has 32 wires coming out of it
8:38so the single pc will have 32 binary
8:41values
8:42we are using bundle representation
8:44because it is really inconvenient to
8:46stare
8:46at 32 wires containing zeros and ones
8:50for a while we would not handle it well
8:52after about five minutes
8:54so we'll see this is a bundle that
8:55represents a hexadecimal value
8:57one zero zero zero corresponding to 32
9:01bits
9:02okay our current address is one zero
9:05zero zero
9:06and the value that we are going to get
9:09at the output of this adder is one
9:12zero zero four okay
9:16that is going to happen after the other
9:18delay so this
9:19adder has a little bit of a delay
9:26the next thing that is going to happen
9:27at about the same time
9:30after the access time
9:33of the memory we are going to get
9:37a value at the output of the memory that
9:40value
9:43here is the new instruction
9:47that instruction is another 32-bit
9:51binary number
9:52but that binary number instead of
9:54writing it a hexadecimal value we did
9:56another shorthand notation
9:57that shorthand notation basically says
10:01that we disassembled it and we got
10:03add x1 x2 x3
10:06as the value on our wires so that's a
10:09fairly straightforward thing
10:10to decode what we need to do is to point
10:13to
10:14parts of that instruction to the
10:16addresses of the register file that
10:18contain rs1 and rs2 and we get the
10:22values
10:23x2 and x3 as the contents of the
10:26registers
10:26x2 and x3 very good
10:30now in the next step we perform the alu
10:32we again have
10:33a bit of a delay there that corresponds
10:35to the addition delay
10:37and at the output of that register
10:41that alu we get the new value
10:44after a propagation delay so some of the
10:47values of register
10:492 and register 3 is sitting on these
10:52wires
10:53but it is not getting written into the
10:57register file for a while it'll get
10:59written on the next
11:01clock tick on the next rising edge of a
11:03clock so the next rising edge of a clock
11:08we store the values of ridge two and
11:10range three
11:12into the register file
11:16so simultaneously as we are updating
11:19that value in the register file that's
11:23when we are writing
11:24the new address into the program counter
11:28one zero zero four and we are continuing
11:30to execute the next instruction
11:32in the same order
11:37well the next that next instruction
11:39better be an ad because we don't know
11:40how to execute anything
11:42else we're going to see how we execute
11:44other things
11:45after a bit of a break see you then

About this transcript

This page contains the full transcript of [CS61C FA20] Lecture 18.3 - Single-Cycle CPU Datapath I: R-Type Add Datapath by CS 61C Departmental, generated from the public captions YouTube serves with the video. The transcript has 1,715 words across 299 segments, with the original timestamps preserved so you can click any line to jump to that moment in the embedded player.

What you can do with it

Use the transcript to take notes, quote the speaker, build a study guide, generate a summary with ChatGPT or Claude via the YouTube Summary tool, or export it as a timed subtitle file with YouTube to SRT. You can also re-open it in the transcriber to translate the transcript into 100+ languages.

Free YouTube transcript tool

YouTube2Text is a free YouTube transcript generator — no signup, no daily limit. Paste any YouTube link and get the full transcript instantly, with timestamps, click-to-jump, translation to 100+ languages, AI prompts for ChatGPT, Claude, and Gemini, and exports to TXT, SRT, VTT, or Markdown.