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[CS61C FA20] Lecture 18.2 - Single-Cycle CPU Datapath I: Building a RISC-V Processor — Transcript

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0:01[Music]
0:11welcome back to our
0:12module on designing a risk 5 cpu
0:16cpu is a digital system so based on the
0:20fundamental principles of designing
0:22digital logic
0:23we should be able to build one but how
0:26do we really go about
0:28building a cpu we have
0:31heard about state machines as a common
0:34way
0:35of describing digital logic or digital
0:38systems
0:39to be more precise so can we use a state
0:44machine
0:45to describe the cpu or to design a cpu
0:50it shouldn't be a surprise that the
0:52answer is yes
0:54we can view a cpu design as design of a
0:56state machine
1:00let's think of one instruction and then
1:02we can
1:03try to extrapolate that to all the
1:06instructions
1:07that we have in a cpu so state
1:11in a cpu is contained in the registers
1:14the memory and the program counter
1:16we don't have any other part of a cpu
1:20that
1:20stores you know source the data
1:25so that would set what would
1:28be combinational logic doing so for
1:30example
1:31in this case if we're doing an addition
1:33operation
1:35all relevant contents would be
1:39in the instruction memory that we have
1:41over here pointed
1:43we wouldn't care much about the contents
1:45of a data memory which is dmem
1:47but we would care about the registers
1:50and the program counter
1:54the contents of the registers and the
1:56program counter in the instruction
1:58memory
1:58would be used to perform the function to
2:02execute that instruction so if the
2:03instruction is
2:04a register based ad then this
2:06combinational logic
2:08would perform an ad based on the
2:11contents
2:12of the state elements
2:15and the result will be written back
2:19into the state elements into the
2:21registers and the memory
2:22and would update the program counter
2:26we can have a different bubble of
2:28combination logic
2:30for every instruction and one can
2:32imagine that we could build really a
2:34processor that way you know every single
2:36one of these 30 something instructions
2:38in rv32i
2:39would have its own delegated bubble of
2:41logic
2:42and then we would essentially use
2:45multiplexers
2:47and the select input on those
2:48multiplexers would be a type of
2:50instruction that we are executing
2:52and we would be updating the state based
2:54on these
2:57different outputs of these different
3:00combinational logic marks but that's not
3:01practical because
3:04many instructions are going to share the
3:07same data path
3:10so in general we are going to try to
3:12build this data path as a cloud
3:14of logic that can execute all the
3:16instructions so
3:18the instruction would would start
3:20executing
3:21on a tick of a clock on a rising edge of
3:24a clock
3:25go through the combinational logic
3:29and present the outputs of it back
3:33to the state elements on the next click
3:36could take overclock on the next rising
3:38edge of a clock we'll write it back
3:41as a new state in the state elements
3:44we'll keep doing that
3:46we by doing that sequence we would
3:48execute
3:50all instructions that we have now
3:54building one monolithic cloud of logic
3:57that would be executing all
3:58instructions is also not practical
4:03it's really hard to think of it that way
4:05it is hard to
4:06to to design that kind of a logic
4:11there is just too much stuff going on in
4:13there so
4:14a general solution to that is to break
4:17up
4:18instruction execution into phases and
4:20have
4:21a bubble of logic associated with each
4:24of these phases
4:26it's a lot easier to divide and conquer
4:28this particularly given
4:30the fact that all instructions have
4:33similar phases
4:35not all of them have all the phases of
4:37execution
4:38but most of all of them have at least
4:41some phases of that execution so
4:43to actually see what that what am i
4:45talking about let's take a look at
4:46common
4:47phases of execution that would
4:50correspond
4:51to separate stages in a data path
4:55so stage one would be instruction fetch
4:58stage two is instruction decode stage
5:01three is execute
5:02stage four is memory access and stage
5:05five
5:06is right back to registers what does
5:08this mean
5:09we're going to see it in a much more
5:11detail
5:12a bit later but i'll just give you a
5:14quick preview for now
5:16instruction fetch gets the instruction
5:19from the memory and
5:24stores it in a processor then
5:27instruction decode
5:28looks at that process that that
5:29instruction and
5:32determines what it is so decodes what is
5:35the operation that you would like to do
5:37in the execution stage
5:39we actually perform the operation
5:42commonly that may be done by the
5:46arithmetic logic unit and we'll find out
5:48that we are
5:49using arithmetic unit not just for
5:53calculating arithmetic and logic
5:55operations whether they're registered or
5:58immediate based but also for branches
6:03then in the fourth phase we would access
6:05the memory
6:06if we're doing any of these instructions
6:09that
6:09have to deal with the memory we would
6:11access the memory in the fourth stage
6:12these are
6:13loads and stores and finally
6:17in the fifth stage if we need to write
6:20back the content in
6:22in the registers like for example in
6:24case of loads
6:25we would complete this instruction in
6:28the fifth stage
6:30by writing back to the register
6:35let's take a look at schematically how
6:37does this look like
6:38so here is a diagram of
6:41a data path for a processor it's a very
6:44generic data path
6:46and it is shown here arranged
6:49are the the elements that we have seen
6:52before
6:52we have heard before but we haven't seen
6:54them really connected in a particular
6:56way
6:58um in the first stage we have a program
7:01counter
7:03then there is an instruction memory
7:05there is a register file
7:07alu and the data memory and in this case
7:11we are assuming that we have two
7:13separate memories
7:15instruction memory in the data memory
7:17although there are part of one physical
7:19memory but we
7:20are assuming that we are separately
7:23treating
7:24that part of the memory that contains
7:26instructions
7:28from a part of a memory that contains
7:29the data we'll see
7:31later why do we do that and how do we do
7:35that
7:38so um just to to get a little bit about
7:41the insight of what is going on in here
7:44um
7:44around there is some logic around the
7:46program counter so the program counter
7:49in when it is executing
7:52instructions in sequence will be
7:55incremented by four
7:56bytes to point to the next 32-bit word
8:00in risk 5. this mux here
8:03is to bypass that increment
8:07and write a branch target if the branch
8:11is to be taken in that way
8:14the program counter would be pointing to
8:16the instruction
8:18where the branch lands
8:21then we have an instruction memory that
8:25has instructions in there
8:28and these instructions will point
8:32to the registers that you would like to
8:34to work with so it would issue addresses
8:37that correspond to the destination
8:39register or
8:41first and second source registers
8:43finally we have the alu
8:46and the data memory and from the data
8:49memory
8:50there is this path where we write back
8:52to the registers let's take a look at
8:54the phases of
8:56execution and they're executed in
8:59sequence
9:00from the first one to the fifth one
9:02instruction fetch
9:04happens by the program counter pointing
9:06to the instruction memory
9:08that is all what it is about the fetch
9:10instruction pointer points to
9:12an allocation in the instruction memory
9:14where the next instruction is
9:15that's how we fetch the instruction then
9:18when we have that instruction
9:21we decode it um often
9:24that phase is associated with the
9:26register read because at the same time
9:28we know that our our formats of the
9:31instructions are rigid
9:33and particular parts of the instructions
9:35are going to be used
9:37as addresses to the register file
9:41in the third phase or stage
9:45of execution we
9:49will execute we will perform addition or
9:52subtraction
9:53or branch calculation
9:57then we will access the memory by
10:01using the result of the alu
10:05and then finally the result of
10:08the the the result of the memory access
10:11will be written back
10:12into the register file
10:15we're going to see this in much more
10:17detail in many many examples for
10:20every single one of the instructions or
10:22instruction types
10:23that we have introduced previously
10:28for now it is important to
10:31also understand this concept of a single
10:35cycle data path so all of these five
10:39phases of execution are going to happen
10:41during one clock cycle
10:43so on a we are going to start
10:45instruction execution
10:46on the first rising edge of a clock with
10:49the instruction fetch
10:50and we are going to write back the final
10:54result on the next rising edge of a
10:57clock
10:57so that at that point the registers will
11:00be updated
11:02and the program counter will be updated
11:05to contain the new
11:06address of the next instruction to be
11:08fetched
11:11later on we'll find out that we can
11:13break this up into multiple clock cycles
11:15but
11:15all of our discussion for the next few
11:18segments is going to be
11:22dealing with this what we call a single
11:24cycle data path
11:25where all five phases of execution
11:28happen
11:29within one clock cycle
11:35so how do we build the data path then we
11:37have seen some of these elements
11:39here are the components that we need we
11:41they're all familiar we have all seen
11:43them
11:44in the module on digital systems so
11:46combinatorial elements that we have
11:49um are adders multiplexers and alus
11:54that will be arranged like legos that's
11:57why this is
11:58so fun because we can do it essentially
12:00as assembling a lego kit
12:03and then we need to complement them with
12:05state elements
12:06which are the elements that store the
12:09data
12:10and the clocking methodology and for now
12:13we are sticking with a very simple
12:15clocking methodology that corresponds to
12:18a single cycle cpu
12:21let's talk a little talk a little bit
12:23about
12:24these state elements the first one that
12:27we'll definitely need
12:28is a register this register is
12:32again a fairly simple structure and we
12:34have seen it before
12:35it's a collection of flip flops if you
12:37will
12:38so a 32-bit register will consist of
12:4232 flip-flops and they're all going to
12:44be
12:45written together on the rising edge of a
12:48clock
12:48so in this case we have data in
12:52port into that register and data out
12:55port in that register we are labeling
12:59it as having a port that is in bits wide
13:03you know what does that mean well it is
13:06a shorthand notation
13:07for having n wires and most commonly
13:10in 32-bit data paths that number n
13:14is going to be 32.
13:17so we have data port that is 32
13:20wires wide into the register and data
13:24out port that is also 32 bit
13:27bits wide the register
13:31gets updated only on the rising edge of
13:33a clock so the new value gets
13:35written on the rising edge of the clock
13:38if
13:39the write enable signal is asserted
13:45if the the write enable signal is not
13:48asserted this if it is d asserted if it
13:50is equal to zero
13:52that the the values in the register will
13:54not change
13:56so let's recap that one more time
14:00we will change
14:03the values of the data on the port
14:07or bus data in
14:11on the rising edge of a clock that new
14:14value
14:15those new values will be written into
14:17the register
14:18and they will stay at the output of that
14:21register until the
14:22next clock cycle and that's it
14:27the next thing the next building block
14:30in this hierarchy
14:32is the register file register file is a
14:34collection of registers
14:36so register is a collection of flip
14:37flops register file is a collection of
14:40registers so
14:41in rb32i we need a register file
14:45with 32 registers to hold all the
14:47registers that we need
14:49for our architecture
14:53one thing to keep in mind that
14:56there is a limitation on how many
14:59registers we can access
15:00at a time um the wires
15:04you know when you get to the really
15:06integrity details of how we implement
15:08processors we'll find out that wires are
15:11a real
15:12challenge to fit to access in any
15:15possible
15:16order these registers
15:20in the architecture of risk five
15:24requires that we should be able to read
15:27two registers simultaneously out of a
15:30register file
15:32and that we can write to one of these
15:35registers
15:38so in short this would be called
15:41to read single write type of a register
15:45file
15:46to read single write
15:50the way how we access the register file
15:53is again
15:54by using the addresses and the buses
15:58there is one input bus that contains
16:01the new value that is going to be
16:03written in
16:04it and it is in risk five rb32i
16:0832 bits wide and there are two output
16:10buses
16:11bus a and bus b that will
16:14contain the
16:18the values that are in registers a and b
16:20or source registers
16:221 and 2.
16:25the way how we select which one of these
16:28two
16:29which of the 32 registers
16:33would put their data out on
16:36the bus a or bus b is by
16:40setting their addresses at these ports
16:43r a and rb
16:46so so when we select when we put a 5-bit
16:50number that corresponds to
16:52a 5-bit address of any of the 32
16:54registers
16:55on ra we are going to get the contents
16:58of that register
16:59on the bus a and correspondingly when we
17:02put an address over register
17:04on port rb we are going to get its
17:07contents
17:08on the output rp when we would like to
17:13write to a register we need to
17:16enable it for writing we don't want to
17:18scribble over the registers accidentally
17:20so we have to say that we mean it by
17:22asserting the right enable
17:24by putting the datum on the bus
17:27w setting the address of the register
17:30that we would like to write into
17:32on rw and the rising edge of the clock
17:35this
17:35value from bus w is going to be
17:37transferred to
17:39the corresponding register
17:44this is kind of a bit of a magic
17:47register file
17:48um we need only clock
17:52to write into it well we assume that
17:54every time we just assert
17:56the when as soon as we put the values
18:00our a and rb at its inputs at the edits
18:04at its address inputs the outputs are
18:07going to show up
18:08so we don't need a clock in order to
18:10read the register file
18:15there is of course some delay until
18:18these outputs show up
18:19we call that the access time
18:23then there are more state elements
18:26elements that contain the states we
18:28so we have a memory and memory is again
18:31fairly magical
18:34we have data in bus and date outbus
18:37and the address we also have a clock and
18:40write enabled it work
18:41very similarly to what we have had
18:43before
18:44so in this case we have multiplex
18:48read and write access to the memory what
18:51does that mean
18:52when we put an address here we
18:55and don't clock it the data will
18:58magically the corresponds to that
19:00address
19:00show up at the date outpus when we would
19:04like to write into the memory we will
19:05assert the right enable
19:07and on the next rising edge of a clock
19:10data in
19:12will be written into a corresponding
19:14memory location
19:16where the address corresponds to
19:23again there are delays associated with
19:25reading and writing the memories which
19:27we'll call
19:28read and write access times when needed
19:33so let's recap what is the state that is
19:36required by the rb32i isa
19:41each instruction during execution
19:46reads and updates the state of three
19:49sets of elements registers the program
19:52counter and the memory
19:54so registers or the register file
19:57holds 32 registers each
20:01being of 32 bits wide meaning that we
20:04have 1024
20:06total flip flops that are organized in
20:0932 registers where each of these 32
20:12registers is 32 bits wide
20:15the first register that you would like
20:16to add address or work with
20:19is specified by the rs1 field in the
20:22instruction the second register that you
20:24would like to read from
20:24is specified by the rs2 field so we have
20:28two
20:28read ports the right register or the
20:31destination where we would like to write
20:33the result
20:34to is specified by the rd field
20:37in the instruction and
20:41we know that x0 register is essentially
20:43a zero so we actually don't need to have
20:46flip flops in that row of the register
20:48file
20:49we can just connect all of those to zero
20:53we'll be anyways ignoring any request
20:55right
20:56there the next one
20:59the next state element is the program
21:01counter it's also a
21:0232-bit register that holds the address
21:05of the current instruction that we are
21:07executing
21:08and we are going to update it during the
21:10execution of every instruction to point
21:12to the next instruction that will be
21:14executing whether it's the next
21:16instruction
21:16sequence which is four bytes away or the
21:19target of a branch
21:21finally we have memory and we hinted
21:24that
21:25we when we are
21:30designing memory it's a monolithic piece
21:32where we store both
21:34the data and the program but for the
21:36purpose of designing a data path
21:38we break it up into two parts the
21:41instruction memory
21:42and the data memory there's still a
21:46part of the same physical memory but in
21:48all of our drawings we are going to
21:50treat it separately and we'll see a
21:52little bit later in
21:53just the next module
21:57that we enable that by using some pieces
22:01a concept called caches we'll have
22:04separate instruction and data caches
22:07which hold the copies of
22:10the corresponding parts of the main
22:12memory but will be on-chip
22:14and fast to access we are not
22:17going to discuss that for now we'll just
22:20imagine
22:21that we have two separate memories
22:25so instructions are read or fetched
22:28from the instruction memory which we'll
22:30call imem and
22:31load and store instructions access the
22:34data memory
22:35which is the daemon so we're now ready
22:38to actually build our first instruction
22:41we'll do that after the break

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