[CS61C FA20] Lecture 15.4 - State, State Machines: Pipelining for Performance — Transcript

Full transcript

1. 0:00and welcome back now let's think about
2. 0:02how to improve
3. 0:03the performance of a system using
4. 0:05pipelining
5. 0:07so again let's talk about this maximum
6. 0:09clock frequency how small can we make
7. 0:11our period how fast can we make our how
8. 0:13high can we make our frequency
9. 0:15so we think about the delay through a
10. 0:16circuit here's a standard circuit but
11. 0:17not tilted on its side
12. 0:19um we've got the idea that
13. 0:23first thing that happens like what
14. 0:26happens at dawn
15. 0:26what happens at dawn is clock
16. 0:30goes high that clock is going to go high
17. 0:33and that rising edge of the clock starts
18. 0:35the whole day in motion
19. 0:36the first delay we see is t clock to q
20. 0:39how long until i see that output on the
21. 0:42inputs whatever
22. 0:43it turned around grabbed its stuff and
23. 0:44then it's available the
24. 0:46queue is stable with whatever the
25. 0:48previous state was
26. 0:50i've got a delay we're going to assume
27. 0:52that this wire has no
28. 0:54delay so maybe on an exam we might say
29. 0:56well assume there's a wire delay
30. 0:58but for now and by default there's no
31. 1:00delay on the wire so the next delay you
32. 1:01see
33. 1:02is t tau sub combinational logic
34. 1:05whatever the conventional logic delay is
35. 1:07there might also be a delay because this
36. 1:08input may not be synchronous we talked
37. 1:09about that before as well
38. 1:12next we've got the this line which is t
39. 1:16setup we got to have that stable t clock
40. 1:18to q
41. 1:19plus t sub cl stable before
42. 1:22t set up before the next rising edge so
43. 1:25in fact
44. 1:26we think about our max delay as being
45. 1:28clock to q again
46. 1:29clock to queue here that's the first
47. 1:32delay you see
48. 1:32the cl delay here and our setup time
49. 1:35which is the last thing that happens and
50. 1:36that all that has to fit into one period
51. 1:38okay so
52. 1:42we saw this idea that you were we had a
53. 1:45register
54. 1:46and then you have here is an adder and a
55. 1:48shifter
56. 1:49okay so this we're going to have now two
57. 1:51elements and the
58. 1:52way i think about this is imagine a
59. 1:54assembly line and
60. 1:55lucy is working on assembly line and
61. 1:57she's got to do something she's got to
62. 1:59wrap
63. 1:59the chocolates and she's got to write a
64. 2:00little poem a little haiku on it at the
65. 2:02same time
66. 2:03and she has to complete successfully
67. 2:05before she can pass it on well
68. 2:07that means the assembly line is going to
69. 2:09have to wait till she can do both of
70. 2:10those things
71. 2:11in the worst case okay next one do the
72. 2:14wrapping and then the haiku
73. 2:16that's a lot that's like the adder and
74. 2:18the shifter couldn't you
75. 2:19have another person who then does the
76. 2:21haiku then you're dividing her work
77. 2:23into two pieces and now you divide it up
78. 2:26but now
79. 2:26i she it takes a little longer right now
80. 2:28rather than going
81. 2:29from let's say brand new chocolate to
82. 2:31one lucy and out
83. 2:33i'm now gonna have to figure out well
84. 2:35can i divide lucy's job into two pieces
85. 2:37and then maybe have somebody to help
86. 2:39divide the load help share the load with
87. 2:41that
88. 2:42and maybe it then goes to the next stage
89. 2:43so it might be longer before the
90. 2:44chocolate gets out
91. 2:45because it's there but the the frequency
92. 2:49is faster the time
93. 2:50between i can get to the the next chunk
94. 2:52the time between
95. 2:53the period is shorter so here's the idea
96. 2:56i gotta register the clock goes high
97. 2:59remember we saw this before the clock
98. 3:01was high i wait ti i wait t
99. 3:03clock to q before i see that output on
100. 3:05my inputs
101. 3:06then i have this really big combination
102. 3:09combinational logic delay this is an
103. 3:11adder shifter delay in this case
104. 3:12and until that's stable and then all
105. 3:15that has to be
106. 3:16stable t setup before the next rising
107. 3:19end of the clock
108. 3:20okay so my clock period is limited by
109. 3:23that huge
110. 3:24you know it said those three terms add
111. 3:26to the the
112. 3:27the minimal the middle clock period is
113. 3:29those three terms
114. 3:31well one of those terms is really big
115. 3:32then that means that minimum is really
116. 3:34big
117. 3:34could i do anything about that and
118. 3:36that's the idea of pipelining
119. 3:38what if i inserted another register here
120. 3:41in the middle
121. 3:42oh my gosh now i'm taking lucy's job of
122. 3:46wrapping
123. 3:46and doing the haiku and doing a separate
124. 3:48thing here again an adder and a shifter
125. 3:50so now what's our timing rising edge of
126. 3:54the clock
127. 3:55now my inputs are available after clock
128. 3:56to queue sitting here on the adder
129. 3:58now i've got my adder delay which is
130. 4:01much smaller
131. 4:02this added delay better be done before t
132. 4:05setup before the next rising edge of the
133. 4:06clock and then it goes to the next stage
134. 4:10and the next stage i've got t clocked to
135. 4:12q t
136. 4:13clocked to cube before that avail that
137. 4:15number is available to s of i minus one
138. 4:17so here's
139. 4:18t clock to q okay there's this
140. 4:22now i've got a delay between when s of i
141. 4:25minus one
142. 4:25pass it to the next level and that's t
143. 4:27shifter delay so that's right in here is
144. 4:29my t shifter delay and again that's
145. 4:31smaller than shifter plus t adder and
146. 4:34again that has to be all stable
147. 4:36before oops that's not drawing a
148. 4:38straight line there but stable before
149. 4:40t set up for the next guy so we love
150. 4:43this i have more outputs per second
151. 4:45but you're paying a price so it's like
152. 4:48you're paying a price that
153. 4:49for one particular chocolate for one
154. 4:51data to go through it takes a little bit
155. 4:53maybe
156. 4:53longer for one thing to go through but
157. 4:55overall pipelining means that more
158. 4:57things per second more outputs per
159. 4:58second
160. 4:59we love that so this is the last slide
161. 5:01let's recap some of our terms here
162. 5:03we've got a clock that's our heartbeat
163. 5:05of the system the setup time is the time
164. 5:07before the rise against the clock where
165. 5:08the data has to be stable on every
166. 5:10flip-flop or every register
167. 5:11hold time is where that data has to be
168. 5:13stable after the rising edge of the
169. 5:14clock
170. 5:15clock to queue is delayed before between
171. 5:17when rising edge happens and that data
172. 5:19is quiescently
173. 5:20available at the output ports flip flop
174. 5:23is how you build registers and registers
175. 5:24we're going to use all throughout
176. 5:26building our data path for a working
177. 5:27risk 5 machine
178. 5:28registers are going to hold these data
179. 5:30and only change the values
180. 5:32on the rising edge of a clock or on that
181. 5:34kind of load level or when there's a
182. 5:36reset it'll ignore the input
183. 5:38and then use and reset to zero that's it
184. 5:40all right we'll see the next video