[CS61C FA20] Lecture 15.2 - State, State Machines: Register Details Flip-flops — Transcript

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1. 0:00welcome back now let's dig a little
2. 0:02deeper into what is
3. 0:04in the innards of a register turns out
4. 0:05it's called flip-flops
5. 0:07so let's see what that why they're
6. 0:08called that so what's inside this
7. 0:10register let's lift the hood on this
8. 0:11so let's give it some names and
9. 0:15register is basically an n bit register
10. 0:18is basically n
11. 0:19one bit flip flops that's the idea in
12. 0:22parallel
13. 0:24the input is called data d for data
14. 0:29and the output is q for i think we call
15. 0:31it quiescent it means it's stable
16. 0:33quiescent q for quiescent
17. 0:37so here is d n
18. 0:40inputs d zero through d n minus one is
19. 0:43n outputs of this one bit flip-flop
20. 0:48this clock which is going to say let's
21. 0:51load the register
22. 0:53has to be sent to all of these guys and
23. 0:55this might be the first time to show you
24. 0:56whenever i show a line that isn't
25. 0:59connected i'm going to try to disconnect
26. 1:01it there so that's really important i'm
27. 1:02going to show those lines not connecting
28. 1:05whenever i show a line that is connected
29. 1:07i'm going to draw a circle there to say
30. 1:08that it's connected so if you ever see a
31. 1:09line like this
32. 1:10it's really ambiguous should have gone
33. 1:12underneath and been a gap or should have
34. 1:13been a circle there
35. 1:14so we're never going to try to do that
36. 1:16we're always going to try to make it
37. 1:16very clear which one we meant
38. 1:18so a circle whenever our two lines cross
39. 1:20and they meant to cross it's the same
40. 1:22signal just being
41. 1:23forked out in a way there'll be a circle
42. 1:26there
43. 1:26if it's ever not connected there'll be a
44. 1:28gap okay so just remember that in the
45. 1:30future as you see our lines and
46. 1:31hopefully we'll try to have every single
47. 1:32drawing we ever show you
48. 1:34so these are called flip flops or ff
49. 1:37for short because the name because it
50. 1:39implies that the data is going to flip
51. 1:41and flop between zero and one that's the
52. 1:43idea
53. 1:44these data is q's output and also these
54. 1:47by the way are called
55. 1:47d type flip flop the other kinds of flip
56. 1:49flops there used to be other kinds d
57. 1:51type is now what we talk about okay
58. 1:53so d-type flip-flop so that's how this
59. 1:54is going to work it's d it's n
60. 1:56an n-bit register is n one bit
61. 1:59uh n parallel one bit flip-flops
62. 2:03what's the timing let's actually go dig
63. 2:05even deeper into a flip-flop now this is
64. 2:06important as we start talking about
65. 2:08timing diagrams
66. 2:09so this one is going to be called a
67. 2:12rising edge triggered and there's also
68. 2:14falling edge triggered flip-flops but
69. 2:15we're going to only consider rising edge
70. 2:16trigger flip-flops
71. 2:18in this this is also called positive
72. 2:19edge which means when it goes from zero
73. 2:22to one that's what it's going to trigger
74. 2:24it means load okay
75. 2:26so let's actually read this so it says
76. 2:27on the rising edge of the clock
77. 2:29the input d is sampled remember here i
78. 2:31am going to use my flip flop
79. 2:32i'll be a one bit flip flop one bit flip
80. 2:33flop on the rising edge of the clock
81. 2:36i turn around i sample i grab what the
82. 2:39input d
83. 2:39is and i transfer it takes some time now
84. 2:42to transfer it to the output now it's a
85. 2:45zero turn around
86. 2:46it goes high okay load load me clock go
87. 2:49up now it's a zero now i'm a zero okay
88. 2:51that's why this happens
89. 2:52at all of the times it's ignored i kind
90. 2:54of started before it's ignored the
91. 2:55input's changing i don't care
92. 2:57i'm not looking at you only when i'm
93. 2:59asked to load
94. 3:01and that rising edge happens right turn
95. 3:02around and grab the value and have it on
96. 3:04the output that's the idea
97. 3:06so here's an example waveform okay let's
98. 3:07take a deeper dive to this waveform now
99. 3:10so i've got a clock rising edges let's
100. 3:14look at this rising edge
101. 3:15right so this is the magic time okay
102. 3:17rising edge rising edge
103. 3:19and notice d is changing right
104. 3:22and d can change all it wants to q
105. 3:25i draw like this this is the way to draw
106. 3:27it to indicate
107. 3:28i don't know what it was it could have
108. 3:30been a one could have a zero i kind of
109. 3:31shaded inside of it it's almost like a
110. 3:33filled in area i don't know what it was
111. 3:35before unknown it's like garbage right i
112. 3:37think
113. 3:37q is garbage and only when
114. 3:41there's a rising edge do i turn around
115. 3:43and grab it so let's actually take a
116. 3:44look
117. 3:45there's my rising edge and i see
118. 3:48a little bit of delay remember there's a
119. 3:49delay in all these devices
120. 3:51between when i grabbed it turn around
121. 3:53grab it and then
122. 3:55show it in the outside so i don't know
123. 3:56what it was but there was even after
124. 3:58this time
125. 3:59i still didn't change it and only after
126. 4:01a certain amount of time
127. 4:02am i going to guarantee to have a steady
128. 4:04state value of whatever the input was
129. 4:06back at that time
130. 4:07at the time zero at that rising edge and
131. 4:09this happens again if i watch this again
132. 4:11let's keep doing this
133. 4:12there's my rising edge i sample d i see
134. 4:15the output on q
135. 4:16rising edge sample d put it on q and
136. 4:19watch it here
137. 4:20what happens i even do it if d hadn't
138. 4:22changed look d is changing between those
139. 4:24two clock guys
140. 4:25look d change in the middle but from the
141. 4:27point of view of the flip-flop i don't
142. 4:28care
143. 4:28because last time i sample it and now i
144. 4:31stay the same so nothing from my point
145. 4:32of view i
146. 4:33grab it zero turn around d is changing
147. 4:35one zero one zero
148. 4:36turn around if it's still zero i just
149. 4:37grab the zero and give it again but i
150. 4:38mean the output should not see it it'll
151. 4:40still be zero throughout that whole
152. 4:41period or that on the output side
153. 4:43okay so far all right
154. 4:47now let's this is one of my favorite
155. 4:48slides this and we'll stop this lecture
156. 4:50series with this slide
157. 4:52the timing is really important to
158. 4:54understand these new words i'm teaching
159. 4:55you some new words today
160. 4:57we saw this rising edge triggered flip
161. 4:59flop we saw that that line nothing
162. 5:00you've seen this already this is
163. 5:02this is all from before this is all from
164. 5:03before let's actually dig into more
165. 5:05detail of this
166. 5:07so the red line is the red line
167. 5:10is the rising edge of the clock that's
168. 5:12the important red line
169. 5:14and now here's the key you're going to
170. 5:16say well dan
171. 5:17can d can d just while i'm trying while
172. 5:20i'm turning around and grabbing it
173. 5:22can d just be moving around like
174. 5:24wouldn't you kind of possibly grab a
175. 5:25half
176. 5:26if it's moving from zero to one and the
177. 5:28answer is yes
178. 5:29i could be in a really unstable state if
179. 5:31as i'm turning around to grab d
180. 5:33d is changing so you need to have d
181. 5:35stable
182. 5:36how stable stable from sometime before
183. 5:40the right like
184. 5:40negative time before the rising edge of
185. 5:42the clock and some stable time
186. 5:44after the rising of the clock so in that
187. 5:46kind of key window when i was turning
188. 5:47around
189. 5:48they better be locked in time before now
190. 5:50i'm grabbing it
191. 5:52and now time after better still be the
192. 5:53stable as i'm grabbing a stable value
193. 5:56and having it on my output so
194. 5:59here is negative time
195. 6:02this means we call this setup time that
196. 6:05input d better be stable for
197. 6:07the setup time before the rising edge
198. 6:10and here
199. 6:11is the hold time
200. 6:14from setup which is negative time before
201. 6:16the rising edge to hold time after that
202. 6:18hitch
203. 6:18that better be stable for both of those
204. 6:20time windows and then so that's two new
205. 6:22words and then
206. 6:23and by the way input has to be stable in
207. 6:25that window okay
208. 6:27and then there's a delay between when i
209. 6:30grabbed it and you saw that we saw that
210. 6:31on the last
211. 6:32slide the output we're going to give a
212. 6:33name to it call it clock
213. 6:35right it's it's let's see what should we
214. 6:38call the name the delay is between the
215. 6:40clock
216. 6:40till it's stable at q so it's clock to
217. 6:43cube what should we call it
218. 6:45block to cue so that's what they call it
219. 6:47it's the delay
220. 6:48between the rising edge of the clock and
221. 6:50when it's stable on the quiescent
222. 6:53calm quiescent stable on the output line
223. 6:55so
224. 6:56clock to queue delay okay three names
225. 7:00set up time is negative time hold time
226. 7:02is time after from
227. 7:04kind of the rising edge till when it
228. 7:05needs to be stable so it's stable
229. 7:06between
230. 7:07set up before hold after and independent
231. 7:10of that
232. 7:12grab it the val output queue is not
233. 7:14stable until
234. 7:15after guaranteed after clock two could
235. 7:17happen before then but when you go to
236. 7:19fry's electronics
237. 7:20you're gonna buy a flip-flop you say i
238. 7:22want
239. 7:23here's some numbers there's three spec
240. 7:24numbers spec spec spec numbers in terms
241. 7:26of that
242. 7:27and usually they're really small numbers
243. 7:28picoseconds often and i'm going to say
244. 7:30well
245. 7:30how about this one that's the bargain
246. 7:32bin what's in there well that's with a
247. 7:33really
248. 7:34huge clock to q delay oh how about that
249. 7:36expensive one
250. 7:37yeah that's a really small clock to q
251. 7:39delay right the faster this thing can
252. 7:40operate
253. 7:41the faster you can clock the circuit so
254. 7:43the expensive ones
255. 7:44are and i'm i'm i'm joking about like
256. 7:47going to fry's and getting just a
257. 7:48flip-flop but the point is
258. 7:49you it's harder to design a system that
259. 7:51has small clock to q it's really easy to
260. 7:53design that has a bad clock to queue
261. 7:55so you want to have the smallest clock
262. 7:57to queue you want and
263. 7:58also you want to have small setup and
264. 7:59hold time so the window wanted to be
265. 8:01stable is small
266. 8:02and the the speed at which i can grab it
267. 8:04and have it on the output is really
268. 8:05small so again you want really small
269. 8:07values there for my
270. 8:08for my flip flop in the ideal case
271. 8:12and again this is the beautiful block
272. 8:13diagram of my dq flip-flop
273. 8:16that's the end of this lecture we'll see
274. 8:17the next one