[CS61C FA20] Lecture 11.3 - RISC-V Instruction Formats I: I-Format Layout — Transcript

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1. 0:00[Music]
2. 0:09hi
3. 0:09welcome back to this 5 instruction
4. 0:11encoding we have
5. 0:13just covered the r type instructions
6. 0:15that
7. 0:16perform register to register
8. 0:19arithmetic and logic operations
9. 0:22so let's see how we can support similar
10. 0:25kind of an instruction
11. 0:27which are those that work with the
12. 0:29immediates
13. 0:30ideally we would like to use the same
14. 0:34instruction format
15. 0:35for all possible instructions but that
16. 0:38may not be quite practical
17. 0:41however we would like to reuse the
18. 0:44placement of most of the fields
19. 0:46across different formats so what we'll
20. 0:49see here
21. 0:49we will need a different format for i
22. 0:51type instructions which are our
23. 0:54instructions that work with immediates
24. 0:56but we'll try to see how we can make it
25. 0:58to be similar to the
26. 1:02r type so let's
27. 1:06re review how do the
28. 1:09register paste add is
29. 1:12how does the register based ad
30. 1:14instruction look like
31. 1:15and how does its immediate counterpart
32. 1:18look like
33. 1:19so register based add takes the value
34. 1:22from register rs1
35. 1:23adds it to the value of register rs2 and
36. 1:25stores the result in
37. 1:27the register destination register rd
38. 1:30its immediate counterpart add immediate
39. 1:34takes the value from the register rs1
40. 1:36adds the immediate and stores the result
41. 1:38in the destination register
42. 1:42so what is that immediate coming from
43. 1:45well it has to be encoded as a part of
44. 1:48the instruction
45. 1:49we clearly cannot use all 32 bits in the
46. 1:51instruction to encode an immediate
47. 1:55so we need to use just part of an
48. 1:57instruction what can we
49. 1:58repurpose from the r type well we can
50. 2:00see that
51. 2:02rs2 is not being used so we can use that
52. 2:04but rs2 only has
53. 2:06five bits five bits is just not enough
54. 2:08for
55. 2:09not enough range for an immediate it
56. 2:11would give us only 32 different values
57. 2:14covering the range of signed
58. 2:17integers from -16 to plus 15.
59. 2:21so um we need to add a new
60. 2:25instruction format where we will
61. 2:27repurpose other fields
62. 2:29of of the in in the instruction format
63. 2:34so let's review what we see in
64. 2:37the r type
65. 2:40we have the op code on the bottom then
66. 2:43we have five bits for the destination
67. 2:46register
68. 2:47three bits for func three five bits for
69. 2:51rs1 and rs2 fields each
70. 2:54and then we have the top seven bits
71. 2:56dedicated to the funct7 field
72. 2:59what are we going to do in the i type
73. 3:01instructions
74. 3:02well we already agree that we're going
75. 3:04to repurpose the rs2 field
76. 3:07but we are going to add the funct7 field
77. 3:09for that
78. 3:10to to that so what is going to happen we
79. 3:12drop that
80. 3:13and make one 12-bit field that is going
81. 3:16to be storing
82. 3:16the immediate value
83. 3:20notice that in
84. 3:24r type instructions we use one op code
85. 3:26we are going to have a new op code
86. 3:28for i type instructions also with r type
87. 3:31instructions we're kind of sloppy in um
88. 3:33we didn't use everything that we all the
89. 3:36the bits that we had
90. 3:38in the instruction you know we had left
91. 3:41over some of the funct7 fields we have
92. 3:43to be
93. 3:44careful how are we encoding things for
94. 3:46eye types because if you're sloppy we
95. 3:48will lose
96. 3:49the the range for the immediates one
97. 3:51thing that we will ask ourselves how
98. 3:53many different instructions do we need
99. 3:54to support in this
100. 3:56case there are seven instructions that
101. 4:00we
102. 4:00we have seen so far we are going to see
103. 4:02that we need to add two more
104. 4:03to our base instruction set so we'll
105. 4:05have nine function field
106. 4:07can encode eight different instructions
107. 4:09so we'll use the trick
108. 4:10to add the ninth one but nevertheless we
109. 4:14are now able to support 12-bit
110. 4:16immediates and they cover
111. 4:18a good range that is something that we
112. 4:20are often going to see
113. 4:22in the assembly code this range of
114. 4:25immediates is going to cover
115. 4:27a wide range of say loops
116. 4:32the range of this immediate since it's
117. 4:3412 bits covers
118. 4:354 4 096 values
119. 4:38going from minus 2048 to plus 2047.
120. 4:42keep in mind that since we are always
121. 4:45using that immediate together with the
122. 4:47value from
123. 4:48a register rs1 which has 32 bits
124. 4:52we have to extend sine extend that value
125. 4:54to 32 bits
126. 4:56what is an extension it is an
127. 5:00automatic operation that processor
128. 5:02performs where it extends
129. 5:05that top most significant bit of the
130. 5:07immediate
131. 5:08across all the most significant bits
132. 5:12basically remember that thing where we
133. 5:14smear
134. 5:15that sign bit over all the bits to pre
135. 5:19to preserve the sign of that integer so
136. 5:22if that
137. 5:23sign of the most significant bit of the
138. 5:25immediate is zero
139. 5:26we copy zero if it is a one we copy all
140. 5:30once
141. 5:31keep in mind that sometimes we'll need
142. 5:35wider range than 12 bits of immediates
143. 5:37and we'll see that later that will
144. 5:39use another instruction to cover that
145. 5:43let's take a look an example for the eye
146. 5:46format
147. 5:47so let's take a look at an assembly's
148. 5:50instruction add immediate
149. 5:52x15 x1 minus 50 which takes the value
150. 5:55from
151. 5:56register x1 adds minus 50 and stores it
152. 6:00index 15
153. 6:01is essentially a subtraction because
154. 6:03remember we don't have sub-immediate
155. 6:09immediate types have a different op code
156. 6:12opcode here is 0 0 1 0 0
157. 6:161 1. that is different at what we have
158. 6:18had in r
159. 6:19type or register based instructions
160. 6:24that had 0 1 1 0 0 1
161. 6:271. now what we need to do is to fill the
162. 6:30rest of the fields
163. 6:32so we will put the rd value of 15
164. 6:35in the rd register and rs 1 value of 1
165. 6:39in the rs1 register we'll take a look at
166. 6:41the green sheet
167. 6:42and find the add has a function field of
168. 6:460
169. 6:460 0 which happens to be the same as what
170. 6:49we have seen
171. 6:50in r type instructions finally we need
172. 6:53to encode
173. 6:54the immediate value in the top
174. 6:5812 bits so here immediate is minus 50.
175. 7:02so we need to write two's complements
176. 7:05value
177. 7:06in the top 12 bits of minus 50
178. 7:09which you can verify is is true um this
179. 7:13is
180. 7:13this one has a value 32 16 plus 1 49
181. 7:17plus 1
182. 7:18to get it inverted is minus 50.
183. 7:22let's recap what we have seen of i
184. 7:25format
185. 7:25arithmetic and logic instructions there
186. 7:28is not there are nine of them
187. 7:30seven of them we have seen before
188. 7:33so this is add immediate
189. 7:36x or immediate or immediate and
190. 7:39immediate
191. 7:40shift left logical shift right logical
192. 7:43and shift
193. 7:44right arithmetic all of them immediate
194. 7:46there are two new instructions that we
195. 7:48have here
196. 7:50slti and slti
197. 7:54u slti
198. 7:58compares the value that is in the the
199. 8:00source register with an immediate value
200. 8:03and if the source register is value is
201. 8:06less than the immediate value
202. 8:08sets the destination register to 1.
203. 8:12similarly sltiu does that
204. 8:16with unsigned numbers
205. 8:20take a look at a few interesting things
206. 8:23in this table
207. 8:24first all func 3 fields
208. 8:28are the same as what we have seen in
209. 8:31registers type instructions
210. 8:36that is very convenient that basically
211. 8:39means that we are going
212. 8:40to recycle that part of a microprocessor
213. 8:42that will have to figure
214. 8:43out what kind of an instruction we have
215. 8:45there
216. 8:46then take a look at this way
217. 8:49um what what are we doing with the shift
218. 8:53amounts
219. 8:54the amount of shift is limited to
220. 8:58five bits because if we shift either
221. 9:00left or right by more than five bits
222. 9:02we have already inserted all the zeros
223. 9:04into the register and
224. 9:06you know using larger shift amounts is
225. 9:08meaningless
226. 9:09we are not going to do anything other
227. 9:11than
228. 9:12just keep shifting in zeros so we don't
229. 9:14need to support that
230. 9:16that's why our shift amount is limited
231. 9:18to five bits
232. 9:20and then we have these top
233. 9:24seven bits of the immediate value free
234. 9:26to do something else in this case
235. 9:28we're using bit theory of the
236. 9:30instruction to encode whether we are
237. 9:32doing
238. 9:33logical or arithmetic shift right
239. 9:38which basically means whether we are
240. 9:40sign extending or not
241. 9:42in and not is that it is done in the
242. 9:44same width position
243. 9:45as we have had for the register based
244. 9:49instructions
245. 9:51and that's it there is
246. 9:55that summarizes the i type format
247. 9:58and we are going to move on to
248. 10:02the next section in a bit