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[CS61C FA20] Lecture 11.2 - RISC-V Instruction Formats I: R-Format Layout — Transcript

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0:00[Music]
0:09welcome back to wrist 5
0:10machine language which is our way of
0:13representing assembly instructions in a
0:14binary format such that the processor
0:16can understand them
0:18keep in mind that we don't study this
0:21because we have a particular joy of
0:23staring at binary representations of
0:25instructions
0:26but we do that because it will be
0:28tremendously helpful later on when we
0:31try to
0:31build a processor rs5 processor that can
0:35execute these instructions
0:36we need to be able to speak at a
0:38language that
0:40processor understands because we don't
0:43have another design method we don't
0:45still have a still don't have a system
0:47that where we can do
0:48this computer here is there is five
0:52specification
0:53build a processor for me such that it
0:55meets that spec
0:56may happen at some point but not
1:00quite right now so let's get into these
1:02instruction formats
1:04we have seen that all instructions in
1:07risk 5
1:08fit 32-bit words so each one of them is
1:12going to be play encoded as a 32-bit
1:14word
1:15it is going to follow a very rigid
1:17format which is going to be
1:20somewhat different between six different
1:22instruction types
1:23the first type that we are going to look
1:25at are register to register
1:28instructions for arithmetic and logic
1:31operations
1:32so let's take a look at the r format
1:35layout
1:36in the right our format layout we said
1:39each instructions
1:40is 32 bits wide so it
1:44covers bits 0 to 31
1:47and it has particular fields it is
1:50divided into variable with fields
1:53that sum up to a total of 32 bits
1:57on the bottom on the lowest least
2:00significant bits
2:01we have the op code off code is
2:04seven bits wide and occupies positions 0
2:08to 6 then it's followed by
2:11the binary code for the destination
2:14register notice it's 5 bits wide which
2:16is enough to represent any of the 32
2:19registers that we have in the risc-5
2:22architecture
2:23and occupies with positions seven to
2:26eleven
2:26then it's followed by another field here
2:28this is called func
2:29three three bits wide
2:33twelve to fourteen bit positions then
2:36go follows rs1 and rs2
2:39register fields each are five bits wide
2:42and finally
2:43there is a funct seven field that is
2:46seven bits wide
2:47from 25 to 31. all
2:51register based arithmetic and logic
2:54instructions
2:55look alike we said that before
2:58it always has an instruction the name of
3:01the instruction
3:03then fields one two three where one
3:05corresponds to the destination register
3:07two corresponds to the first source
3:11register
3:11three corresponds to the second source
3:13register and we see that here
3:15we have the the place to
3:19put the which one of the of the
3:21registers is
3:22our destination register and we have
3:24spaces for our
3:26two source registers let's take a look
3:30a bit more what are these op codes and
3:33funct 3 and func 7 fields those are the
3:36ones
3:37that specify what kind of an instruction
3:40do you want to execute
3:41right so op code functs 3 and func 7
3:45are going to tell us whether we want to
3:47do add subtract
3:49shift left or xor and so on
3:53and these are going to be the registers
3:57that we are targeting
3:58notice one important thing all opcodes
4:02all instructions that are of our type
4:04are going to have the same op code
4:07that is going to be 0 1 1 0 0 1 1
4:10every single one of them and and or are
4:13all are going to
4:14to have 0 1 1 0 0 1
4:171 in the op code field that means that
4:20different instructions are going to be
4:22encoded in funct 3 and func 7 fields
4:27but then you you you may scratch your
4:29head oh
4:30um why do i need
4:3410 bits to encode
4:37about 10 instructions i mean with 10
4:39bits i can encode
4:411024 different instructions are we going
4:44to encode them such that
4:45each one of them is just has one bit
4:48equal to one
4:49no but it is true that we don't need
4:531024 we don't need to utilize all funct
4:553 and func 7 fields
4:58bits in function and function fields to
5:00represent all arithmetic and logic
5:02instructions
5:03so we have some redundancy there we have
5:05some options how we want to choose that
5:07encoding
5:08and we'll find out that we're going to
5:10use that to make the job
5:12of a processor in figuring out which
5:14extra instruction is it going to
5:16execute easier all right
5:20the other question is why are these you
5:22may ask why are these op code and
5:24functioning and
5:25seven fields spread all over the place
5:29we'll see that later it is again to make
5:31processor job
5:33easier
5:36now we have mentioned that each
5:37instruction has register specifiers
5:40and they're placed at rigid spots we
5:43have a spot for the
5:44destination register for the source
5:46register
5:47and the other source register
5:50each uh register holds a five bit
5:54unsigned
5:54integer which is just enough that we
5:58need
5:58to identify one of the 32 registers that
6:02we have in the
6:02s5 ic so there is no redundancy there
6:05and no need to have any redundancy there
6:07so let's take a look at a practical
6:09example how we do that
6:12let's encode the first instruction that
6:14we have learned for register based
6:15operations that's the add
6:18and the format of the ad is add rd rs1
6:21rs2 so in this case add will operate
6:25on the contents of the register 6 19 and
6:27x10
6:29take them and them together and place
6:30the result in the register destination
6:33register x18
6:35so what we have here is
6:40relatively straightforward when you look
6:42into it first we are going to take
6:44write down the op code all r type
6:47instructions
6:48have the same opcode that opcode
6:51is 0 1 1 0 0 1 1
6:54then we're going to look up in the green
6:56sheet and find out
6:58that add instruction corresponds to all
7:01zeroes
7:02in funct seven and func three fields
7:06and then finally we need to fill out the
7:08numbers that correspond to the registers
7:10that we are using
7:11so in this case we look up where does
7:14the destination register x18 go
7:17oh it's supposed to go into the rd field
7:19so we
7:20write the binary value for 18 which is
7:23one zero zero one zero sixteen plus two
7:26all right we got that one and we do the
7:29same
7:30with rs1 and rs2 registers rs1 is 19
7:33which is 16 plus 2 plus 1
7:36and then finally rs2 right here
7:40is 0 1
7:430 1 0 which is 10.
7:46all right we figure that out hopefully
7:48that made sense
7:50how about you do this one and
7:53what is the correct encoding of add x4
7:55x3 x2
7:57and ignore that i might be using some
8:01reserve registers for some things this
8:03is just an example
8:04of register based edition
8:08i'll pause here or you can pause me here
8:12do it yourself and then i'm going to
8:15continue
8:16and work it out in this case we actually
8:19don't need to
8:21write all 32 bits let's try to guess
8:24which one
8:25is is right the correct representation
8:29so let's take a look first
8:32all register based instructions
8:35end with 0
8:390 1 1 which is a hexadecimal
8:42representation
8:43of 3 and notice that all our answers
8:46are offered here as hexadecimal numbers
8:50so i should just go ahead and eliminate
8:53the one that does not end with three
8:58the other ones we have no options the
9:00next
9:01significant digit to be either three or
9:04b
9:04which one is that so let's take a look
9:06at our drd is x4
9:08the last bit of x4 is zero
9:14x4 is zero one
9:18zero zero so then it has to be
9:21if i take these bottom three bits and
9:24add a zero that is that has to be
9:26here then that's going to be zero zero
9:30one one
9:31therefore the next significant bit needs
9:34to be
9:34three as well so you can cross these two
9:37off
9:38so which one is it four zero two one
9:42or zero zero two one well we
9:45know that add
9:50has all zeros in the leading position so
9:52we can eliminate this one
9:55and four is our correct answer but if
9:57you would like to
9:58to verify that you can go ahead and
10:01write down
10:02all 32 binary digits
10:05and convert them to hexadecimal it's a
10:07short exercise
10:10well this is a summary of all
10:14of our r type instructions we have seen
10:17them all
10:20we have the the encoding for all of them
10:23in one table so what we find out they
10:27all have the same
10:29op code in the end so zero one one
10:33zero zero one one and they have they
10:35have
10:36the same spots for the destination and
10:38the two source registers
10:40and they have different funct seven and
10:43func three fields
10:46so the instructions that we have here
10:48are
10:49add sub sll slt
10:53sll stands for shift left logical what
10:55is slt
10:58it's a new instruction it is set
11:02on less than it compares the values of
11:06registers
11:08source registers rs1 and rs2 and if
11:10contents of rs1
11:12is less than rs2 it sets the destination
11:15register to 1.
11:17it is useful for comparisons there and
11:19then there is the unsigned version of
11:21that
11:21then we have xor shift write logical
11:25shift right arithmetic or an end so we
11:28just added two more
11:30instructions over here that are very
11:31useful
11:33let's take a look a little bit at the
11:35encoding here
11:37um one thing that you will spot is that
11:42add and sub are very similar to each
11:45other
11:46and that's done on purpose that way
11:47because we are going to be using
11:50the same hardware to perform subtraction
11:53as we use for addition because
11:56subtraction is just
11:58using two's complements number addition
12:00of two's complements number there is no
12:02different hardware needed
12:04except that we need to perform sign
12:07extension
12:09so go ahead and circle this
12:13this bit basically says that i need to
12:17sign extend
12:19an operand before i perform subtraction
12:22whichever instruction
12:23has that bit equal to one
12:26this one what's that instruction oh
12:29that's shift right arithmetic that's the
12:30another one that does the sign extension
12:32so this
12:33bit here signifies that instruction
12:38is going to do sign extension
12:46it basically tells a processor
12:49you're doing register type instruction
12:53and you're supposed to
12:56start with sign extension here so very
12:59early on
13:00it can start extending the sign of the
13:02operand
13:04very useful hint over there and
13:07then you're going to see some other
13:09similarities through this table
13:10you don't have to pay attention to that
13:12now but there is some cleverness that is
13:14put
13:15in the way how they're encoded i'm going
13:17to pause here and
13:20we back in just a bit to talk about
13:23the next type of the next for
13:27instruction format which is our
13:29immediates
13:31see you there

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