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Beta Gallium Oxide Epitaxial Growth and Vertical Power Devices — Transcript

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0:01Okay.
0:02Hello everyone. My name is Ajay Jacob
0:05and I am the
0:07uh director of projects at the
0:09California Dream Sub.
0:11Today we have
0:12Professor Sriram Krishnamoorthy from UC
0:14Santa Barbara
0:16uh giving us a talk on
0:18beta gallium oxide epitaxial growth and
0:21vertical power devices.
0:23Uh Professor Krishnamoorthy received the
0:25bachelor's degree in electrical
0:26engineering and physics from the Birla
0:28Institute of Technology and Science from
0:31Pilani, India
0:32and a PhD degree from
0:34Ohio State University.
0:36Uh Professor Krishnamoorthy is currently
0:38an associate professor at the the
0:40material in the material department at
0:42the University of California, Santa
0:44Barbara where his group works
0:46at the intersection of materials,
0:47electrical engineering, and physics to
0:49study and engineer next-generation
0:52ultra-wide band semiconductors such as
0:54gallium oxide.
0:55His research interests are in the area
0:57of epitaxial growth, electronic
0:59transport, design, modeling, micro and
1:02nano fabrication, and characterization
1:04of electronic, optoelectronic devices
1:07for a wide range of applications such as
1:09power electronics, high-frequency
1:10electronics, and ultraviolet
1:13electronics, optoelectronics. He has
1:15authored or co-authored publications on
1:17several topics covering gallium nitride
1:19interband tunnel junctions for efficient
1:21hole injection in three nitride
1:23optoelectronic devices
1:25MBE growth of three nitrides, gallium
1:29aluminum oxide thin films and
1:30heterostructures, MOVPE of ultra-wide
1:34band gap gallium aluminum oxide thin
1:36films and heterostructures, and
1:38high-performance lateral and vertical
1:40power device and transistors based on
1:42gallium oxide. So, it's my pleasure to
1:44invite uh Professor Krishnamoorthy to
1:46the stage.
1:47Go ahead, uh
1:49Sriram.
1:50>> Thank you, Ajay. Uh very excited to
1:52share our recent uh about our recent
1:55research efforts in
1:56uh beta gallium oxide of production
1:58growth and vertical power devices.
2:01A huge shout out to my team here in
2:03UCSB. We work closely with Professor Jim
2:05Speck
2:06in the materials department as well.
2:08And I would like to thank our
2:10collaborators, Kyma Technologies,
2:13a national labs, AFRL, US Naval Research
2:16Lab,
2:17and our circuit collaborators
2:20at Ohio State. I would like to also
2:22thank the funding from ARPA-E program,
2:25the Coherent to 6 Foundation, and also
2:28we have any comments project
2:31through the class hub
2:33in North Carolina. So I'd like to thank
2:35all of the funding agencies for
2:36supporting this work.
2:39So
2:41I think the idea behind
2:44using
2:46wide band gap materials for power
2:48electronics is the fact that when we
2:50increase the band gap of a
2:52semiconductor,
2:54it can generally hold much higher
2:56electric field across it.
2:58So going from the traditional power
3:01semiconductor, which is silicon, to say
3:03silicon carbide and gallium nitride,
3:06you go from couple hundred kilovolts per
3:09centimeter to about 3 megavolt per
3:12centimeter.
3:13And so
3:15as the band gap increases, the breakdown
3:18field
3:19goes roughly as the square of the band
3:21gap.
3:22And so the electric field handling
3:24capability of a wider band gap
3:25semiconductor is significantly higher
3:27than silicon.
3:30So stretching that idea a bit further,
3:32if we go to newer materials like gallium
3:35oxide,
3:36then
3:39we can further have much higher electric
3:41field across the device,
3:43and the on resistance of a power switch
3:47that's made using such a wide band gap
3:49material goes inversely as a cube of the
3:52breakdown field.
3:54And the breakdown field goes square of
3:56the band gap.
3:57So, now we can see there's a huge
3:59advantage in going to wider and wider
4:00band gap materials from a on resistance
4:03perspective. And the most simple way to
4:05think about that is for a given blocking
4:07voltage
4:08we need to support the block voltage
4:11across a much thinner layer as we go to
4:14wider band gap materials.
4:16And that's captured through the figure
4:18of merit, the Baliga's figure of merit
4:20that's shown over here.
4:23So, um
4:25So, when we go from a material like
4:26silicon we can get a very um enhanced uh
4:31trade-off in terms of the on resistance
4:33and the breakdown voltage and we go from
4:35silicon to wide band gap materials.
4:37And our idea here is that if you go to
4:40even wider band gap, the so-called ultra
4:42wide band gap materials, this this
4:44impact can be further amplified.
4:46Um So, that's at a device level, but if
4:49you make a device um
4:51a unipolar device which switches at a
4:53higher frequency then the
4:56inductors and capacitors that are part
4:58of a typical
4:59um power circuit can also go down in
5:02size.
5:03And if the on resistance itself is lower
5:07then the demand in terms of uh heat
5:10sinking goes down.
5:11So, overall at a system level as well
5:13there's going to be huge size and weight
5:16benefit and performance benefit, our
5:18swap benefit. So, that's that's a case
5:21for going to wider and wider band gap
5:23materials.
5:24And why gallium oxide in specifically,
5:27right? So, before that I would like to
5:29also maybe give a use case or um pitch
5:33for why we generally need higher voltage
5:35switches. So, right now the highest
5:37voltage uh
5:38switch that you can get, power switch
5:40that you can get is a silicon IGBT
5:426.5 kV.
5:44Um
5:45and silicon carbide um
5:48uh
5:49power MOSFETs which are
5:50at either 1.2 kV or 3.3 kV range.
5:55So, if you have a high voltage system,
5:58then you need to stack multiple of these
6:01um
6:02uh
6:03modules in series and then control them
6:06synchronously
6:07to be able to realize a high voltage
6:09system. Whereas, if you can go go to an
6:11individual device or module that's rated
6:13at a much higher voltage. So, that can
6:16dramatically simplify the overall system
6:18complexity and the control part of it as
6:21well.
6:21Uh and so so that's another argument to
6:24look for new materials that can support
6:27uh the single device or you know a
6:29module can support tens of kilovolts
6:31instead of stacking multiple modules in
6:33series.
6:35So, this kind of application is
6:38interest is particularly relevant now in
6:41the context of AI data centers.
6:44So, right now the distribution in a in a
6:47data center is at 415 V.
6:50So, 415 V AC distribution that comes
6:53into the rack compute rack and then you
6:55convert that to lower voltages and then
6:57that goes to even lower voltages uh for
7:00the GPUs and TPUs, right?
7:03Uh so, this is a paper from Nvidia where
7:06they envision a future where by going to
7:08a much higher voltage DC distribution.
7:12So, going directly from um
7:14uh 13.8 or say 35 kV AC to a 800 V DC uh
7:20uh
7:21a distribution within the data center
7:24and then taking the 800 V distribution
7:26directly to the compute rack and then
7:28locally doing the power conversion down
7:29to the GPUs.
7:31So, so by going from this 415 V AC to
7:34800 V DC,
7:36uh one can dramatically reduce
7:38uh the conduction losses. Uh so,
7:40basically you reduce the the current
7:42draw, and so that reduces I squared R
7:44loss. And in [snorts] this estimate that
7:46they worked out, um, so that gives about
7:49like a 5% improvement in the end-to-end
7:51power efficiency, which is a big deal,
7:52because 5% off a huge number is still a
7:56very huge number, right? Uh,
7:58and to enable a technology like this, I
8:00think one needs high-voltage,
8:03um, transistors and diodes, because
8:06that's going to go into these
8:07solid-state transformers.
8:09Uh, and so, um, so there is a case to to
8:12develop these high-voltage, uh,
8:14switches,
8:16um,
8:16for any kind of high-voltage system, and
8:18solid-state transformers may be one
8:20example of that. And if you look at a
8:21solid-state transformer, uh, which I
8:24grabbed this picture from the Freedom
8:25Center website, uh, at North Carolina
8:27State University. So, so here you can
8:29see that it's essentially the the heart
8:32of this, uh, is the semiconductor
8:34switches, right? The the transistors and
8:37the diodes. And so,
8:39so
8:40so these power transistor diodes and
8:43transistors and diodes basically are
8:45part of any power converter system
8:47or a solid-state transformer.
8:49And the simplest way to think about
8:51these, uh, power switches is just making
8:54an
8:55making it analogous to a mechanical
8:57switch. So, when the switch is closed,
8:59you want,
9:01uh, close to zero resistance for the
9:03switch, right? So, so the on resistance,
9:06this would be the operating point of,
9:08uh,
9:09in a power transistor in the linear
9:10region. So, you want this voltage drop
9:12to be as close to zero as possible. So,
9:15you need the resistance of the switch to
9:17be as low as possible.
9:19And the off state, uh, would be, uh,
9:21over here. And, uh, so essentially, we
9:24would like to get a high blocking
9:26voltage. And so, a combination of high
9:28blocking voltage and low on resistance
9:30uh, makes makes the switch exciting.
9:33Uh, and this trade-off between this on
9:36resistance and the blocking voltage can
9:39be made much better when we go to wider
9:41and wider band gap materials, right? So,
9:43hopefully I'm
9:45I've given a background of why we need
9:47these switches. And this is where the
9:49gallium oxide gets exciting because
9:51gallium oxide has band gap that's 4.6
9:55electron volts,
9:56much larger than silicon, a bit larger
9:59than gallium nitride and silicon
10:01carbide.
10:03And uh
10:06One exciting aspect of this material is
10:08that
10:09we actually have bulk substrate
10:11technology available. So, these are 6-in
10:14edge-fed grown melt-grown substrates uh
10:18from Japan.
10:19Uh and you can buy 4-in substrates off
10:22the shelf even today, and 6-in should be
10:24like a special order. Uh but essentially
10:27this technique, the edge-fed growth
10:28technique is the same technique that's
10:29used for uh pulling out sapphire from a
10:32melt. And we all know how sapphire
10:34scales well to larger areas, and it's
10:36low cost. And so so eventually, you
10:38know, with enough volume, you know, this
10:40could be a great thing to have a bulk
10:43substrate technology uh that can be
10:45scaled to larger areas because power
10:48devices um
10:50especially the power devices that are uh
10:52required uh for high voltage
10:54applications uh generally also need high
10:56currents. And so
10:58so so so the devices themselves are
11:00going to be like huge, and and having a
11:02bulk substrate platform is going to be
11:03very important. So, it's the only
11:05ultra-wide band gap semiconductor that
11:07can be pulled out of a melt and still
11:09doped n-type. So, you can get n-type
11:11doping control over large range, and
11:13large area substrates are available. And
11:16uh if you make just a
11:17back-of-the-envelope calculation of the
11:19on resistance breakdown voltage
11:20trade-off for gallium oxide, we see that
11:22when you cross 10 kV, this can be, in
11:26theory,
11:2710 times lower on resistance than
11:29silicon carbide. So, that makes it very
11:30exciting. Uh so to so so so at the lower
11:34voltages gallium nitride and silicon
11:35carbide already
11:37uh
11:38doing great. There's There's an
11:39ecosystem out there, and uh and lots of
11:42exciting products are coming out. And so
11:44so we think for a new material like
11:46gallium oxide the use case could be at a
11:47much higher voltage uh that is harder to
11:50access with the current materials. So so
11:54and the other uh important aspect in a
11:57power switch is also the fact that uh
12:00you need to have shallow dopants.
12:02So, shallow doping is very important.
12:04So, when I mean shallow doping what I
12:05refer to is that uh the the energy level
12:08of the dopant below the conduction band
12:10is
12:11comparable to thermal energy. And that
12:13is the case for gallium oxide. So, for
12:15gallium oxide we can actually get
12:17dopants which are just a KT below the
12:20conduction band. And so you actually get
12:23close to 100% ionization efficiency at
12:25room temperature uh for these dopants.
12:28Uh
12:29and that's kind of important because in
12:30other materials like diamond, which
12:32would be the ultimate uh
12:34material
12:35uh in terms of band gap or aluminum
12:37nitride, uh it's harder to get uh
12:40shallow dopants, right?
12:42Uh and so and why is that important?
12:44Because you need
12:46shallow dopants, you need full
12:47ionization at um room temperature for
12:50the on state to get enough carriers to
12:52reduce the resistance of the switch.
12:54Uh but if you don't have a shallow
12:56dopant, then you end up putting lot more
12:58dopants to get fewer electrons.
13:00That's okay. But under reverse bias
13:03these dopants can feel that ionize and
13:05that create a much higher electric
13:07field. And so the trade-off between the
13:10on resistance and breakdown voltage is
13:12actually worse for a material that has
13:14deeper dopants. Okay, this is actually
13:16worked out as a modification to the
13:19standard Baliga figure of merit in this
13:21paper from Jim Speck's group in 2020.
13:23Uh and so So, putting this together it
13:26turns out that gallium oxide is quite a
13:28there's a quite a compelling case for
13:30looking at gallium oxide as the switch
13:32when you cross to much higher voltages
13:34and especially having bulk substrates is
13:37appealing and the shallow dopants are
13:38also appealing.
13:40And and so these are basic ingredients
13:41that that that make the material
13:42exciting, but um
13:45more than that uh a high electric fields
13:49have already been reported in this
13:51material. So so so 4 to 5 MV per cm has
13:55been measured um by multiple groups um
13:59you know, across the US, Japan, and
14:02Europe, and China.
14:03And uh and so this value, this
14:06experimentally measured value of
14:08electric fields in the device
14:10>> [snorts]
14:10>> um is actually higher than the
14:12theoretical field of gallium nitride and
14:14silicon carbide. So the high field
14:16promise is quite there and it's been
14:18seen by multiple groups. So I think
14:20these ingredients make it kind of
14:21exciting to to to to to work on this new
14:23material system
14:25um and to develop uh you know, the
14:27material science, growth, and try to
14:29make a nice high voltage vertical power
14:32switch. So that's been the focus of my
14:34group. So in my group uh we do both
14:36growth and um
14:38and devices. In terms of growth, we use
14:41um this Agnitron Agilis reactor research
14:45reactor 2-in 2-in capability. We use the
14:47standard precursors that are used in
14:49other uh compound semiconductors like
14:51triethylgallium, trimethylaluminum.
14:53And we use ultra high purity oxygen as
14:56the oxidizing precursor
14:57uh and silicon is a dopant uh for
15:00gallium oxide. So silicon is
15:01substitution substituting the gallium
15:02site as a shallow dopant. We use dilute
15:05silane for doping and argon as a carrier
15:07gas.
15:08So so right now the the reactor is
15:10configured with uh about 18 cm distance
15:13between the showerhead and the chuck,
15:14but but you know, we have the capability
15:16of bringing this closer
15:18um
15:19uh
15:19what is referred to as the close
15:21injection showerhead geometry. So,
15:23that's possible, you know, that's part
15:24of our future plans as well.
15:26So, the first thing that's interesting
15:29that we observed in the growth MOCVD
15:31growth of gallium oxide is that the
15:35growth window is actually fairly large.
15:37So, gallium nitride needs at least about
15:391,000 C and higher to crack the ammonia
15:41precursor and have sufficient adatom
15:44mobility on the surface. Whereas here,
15:47gallium oxide
15:49high-quality gallium oxide can be grown
15:51even at temperatures as low as 600 C.
15:54And so, this is
15:55experimentally measured Hall data as a
15:57function of
15:59electron concentration from Hall
16:01measurements. So, we can maintain smooth
16:03surface morphology, a very sharp doping
16:06profile
16:07when we try to grow colder.
16:09And
16:11this can be used to
16:13our advantage in terms of growing these
16:16materials on substrates.
16:18So, typically we grow on insulating
16:19substrates. So, insulating substrate is
16:21it's it's doped with iron as
16:24as a compensated compensating dopant.
16:27And this iron that we have in the
16:29substrate can actually get into the
16:30epitaxial layer. So, so being able to
16:33grow low-temperature
16:36initial layer or nucleation layer
16:39on gallium oxide can help us really drop
16:42off the iron surface riding into the
16:45film to within a tens of nanometers
16:47close to the substrate.
16:49And then, once we do the low-temperature
16:51layer, then we can ramp up the reactor
16:54temperature and grow [clears throat]
16:55high-quality doped layers. Okay. So, so
16:58this having this large growth window for
17:00this material system is quite exciting.
17:02And so, that helps us give get sharp
17:04doping profiles.
17:06It helps us do this kind of engineering
17:10the stack to be able to get high
17:11mobilities. So, so using putting these
17:14ideas together, you know, by figuring
17:16out the surface preparation techniques,
17:19low temperature initial layer, and high
17:20temperature channel layer, we've been
17:23able to get across-the-board enhancement
17:25in electron mobility
17:27in the in this in these in these films.
17:29And you can see the wide range of doping
17:31capability we have,
17:3310 to the 15 to 10 to the 20, which
17:35nicely scales with the flow of silane.
17:38Um
17:39And um so so this helped us achieve some
17:42record results in terms of electron
17:43mobility in the in the channel layer.
17:46And uh these these these channels are
17:48also high electric field handling
17:52capable of handling high electric
17:53fields. So so for instance, with just
17:552.7 microns of gate-drain distance, uh
18:00we're able to block 1 kV.
18:02Uh so that translates to an average
18:04electric field of about 4.2 MV/cm,
18:08uh which is higher than the theoretical
18:10handle electric field handling
18:12capability of gallium nitride and uh and
18:15silicon carbide.
18:17So so so so basically the large growth
18:20window and helps us get high mobility
18:24and we can then translate that to high
18:27handling
18:28electric field handling capability in
18:30these devices.
18:32So um
18:34But but you know, this this these
18:36lateral topologies are okay for for um
18:39lower voltages. Uh eventually we need to
18:42get
18:43to low bulk thick epitaxial layers.
18:47So we need large thickness to be able to
18:49hold um
18:51block higher voltages.
18:53Um and that would then necessitate
18:56uh high purity material. Cuz we need now
18:58the doping to be less than 10 to the 16
19:01uh because, you know, if you have a
19:03triangular electric field profile,
19:05uh then then you need sufficient low
19:08doping
19:09uh and high thickness of the drift layer
19:11to be able to maximize the area under
19:14this electric field curve, right? Which
19:15is basically the blocking voltage.
19:18So,
19:19uh
19:20so so there is a need to develop
19:22techniques that can uh
19:24that can that that that can that can
19:26realize large thicknesses of these
19:27layers with with low doping uh
19:29concentration, negligible compensation,
19:32and high carrier mobility in these these
19:34structures.
19:36So, uh so we started out some of this
19:38effort with MOCVD. So, this is uh some
19:41recent work where we've been able to
19:43grow 4 to 6 micron thick films.
19:47Uh we've been able to reduce the
19:48unintentional background doping in the
19:51material to low 15s, 10 to the 15s. And
19:54then by systematically varying the
19:56silane flow, we can control
19:59uh the doping in the film
20:02below a value that's 1E16. So, these are
20:04super pure, uh more than parts per
20:06billion pure films.
20:08Uh
20:09uh so so
20:11we've been able to demonstrate that
20:12using MOCVD here in UCSB.
20:14And you can see this nice variation uh
20:16of the doping profile as we go to higher
20:20and higher silane flows. And we've also
20:22verified that the the the the cost for
20:25electrons uh in this film is actually
20:28silicon that we have in the film. So,
20:29we've been able to make a one-to-one
20:30correlation between the measured
20:32electrons to the silicon measured from
20:35the SIMS measurement or you know
20:37secondary ion mass
20:38uh spectroscopy measurements.
20:40And we've been able to get uh record
20:43electron mobilities close to 200 cm² per
20:46V-s uh
20:47for the low doping range, 10 uh all the
20:49way from 3E15 to 1E16 uh range.
20:53The reason this is flat is because in
20:55gallium oxide, it's it's a low symmetry
20:57crystal. There are lots of phonon modes.
20:59There's a strong electron-phonon
21:01coupling and uh fully interactions. So,
21:04so the theoretically expected mobility
21:07at the low doping regime is indeed close
21:09to 200. So, we've been able to get um
21:12films that are uh close to theoretically
21:14predicted values in terms of electron
21:16mobility.
21:18Uh
21:19So, so we do have these high-quality
21:21films um
21:22in gallium oxide and if you put that
21:24together in the literature, so generally
21:27in the literature when we get to lower
21:29uh electron density values below 10 to
21:31the 16, uh you start to see a drop-off
21:34in the mobility because of compensation
21:35effects.
21:36Uh but, you know, by carefully tuning
21:38the growth conditions, we've been able
21:39to uh cross that barrier and and get a
21:42much higher electron mobility uh in
21:44these films
21:46uh with intentional doping.
21:49So, uh we've been pushing this further
21:52uh trying to access even uh lower
21:54doping, uh much larger thickness,
21:58uh and so Carl Petersen in my group is
22:01going to be presenting a number of
22:02papers uh in uh
22:04uh uh uh in IWGO. This is basically a
22:07a conference, a workshop uh that that's
22:10scheduled uh in a few months in in
22:13Maryland,
22:14uh in University of Maryland. And uh so
22:17this is a week-long uh workshop uh
22:20where you have attendance from all the
22:22best groups working on this area.
22:24Uh so so so Carl is going to be
22:25presenting uh some more recent updates
22:28to this. So, achieving high uh electric
22:31fields at the junctions up to 4 MV/cm,
22:34translating to high figure of merit, and
22:36also uh growth along a new orientation
22:39of crystal uh
22:41with high purity resulting in uh devices
22:44that can block up to 7 kV using MOCVD.
22:47So so uh and to to be able to achieve
22:50these results, we had to go back and
22:52look at the crystal structure more
22:53closely and analyze uh
22:56the effect of the orientation on process
22:59damage.
23:00Uh and we also learned that certain
23:02orientations are actually more
23:03susceptible to ion damage and so we had
23:05to come up with processes that are less
23:07damaging and so on and so forth. So so
23:09this is going to be presented later
23:12in a few months by Carl and Carl is
23:14actually in the job market so he he can
23:17do growth and devices so be great hire
23:20for anyone in this ecosystem.
23:22Um
23:23Okay and again why why am I emphasizing
23:25this low doping regime because that's
23:27what you need to get to high voltage
23:29devices. So so to get to something like
23:316.5 kV
23:33we need thicknesses in the range of tens
23:35of microns of material with low doping
23:38and and so so getting this combination
23:41is is tricky and in the MECommons
23:44program that we have with the with the
23:47CLAWS hub
23:48Kaiima Technologies um
23:50was the lead for that project they've
23:52been able to get some outstanding
23:53results domestic epi results. Um
23:57So so these are these are being
23:59published very recently in the special
24:01issue on gallium oxide uh just this this
24:04month
24:05and essentially they've been able to so
24:07this is a paper from Carolyn Riley and
24:08Jacob Leach at Kaiima so they have been
24:11able to demonstrate up to 50 micron
24:14thick epitaxial layers using halide
24:16vapor phase epitaxial growth. Uh so so
24:20so so this is work done by Kaiima and we
24:23had access to some of this epi through
24:25our project and we've been able to do
24:27high voltage CV measurements to confirm
24:30that actually
24:32down to more than 10 to 12 microns into
24:35the layer the doping is flat and it's
24:38actually in the mid 15s regime and
24:40that's exactly what you need you need
24:41mid 15s doping and tens of microns of
24:44thickness to be able to hit uh 6.5 kV 10
24:47kV and these higher voltage devices so
24:50lots of exciting progress
24:52in the last few years in terms of the
24:54epitaxial growth capability both in
24:56Japan and in the US.
25:00Okay, so that is
25:03the section in my presentation on
25:05growth. Now, let me switch gears and
25:08talk about some device research in my
25:11group. We do both growth and devices.
25:13So, so we have been trying to make these
25:16high voltage devices using a variety of
25:18topologies
25:20using high K dielectric field plates
25:23using charge balancing techniques using
25:26dielectrics and also geometry
25:32based uh
25:33topologies. So, essentially trying to
25:35make a trench out of the device and
25:37reduce electric field of the device
25:39through careful electric field
25:40engineering and also combining gallium
25:42oxide
25:44with other P-type oxides like nickel
25:46oxide and chromium oxide
25:48uh to to kind of overcome the issue with
25:51gallium oxide that is that there's no
25:54P-type doping available, right?
25:56And even if you found a P-type dopant,
25:59the valence band is very flat, so the
26:01holes wouldn't move much. And even if we
26:04managed to get holes in the valence
26:06band, there is a strong polaron
26:09formation in this material. So, so you
26:10would self-trap the hole and lose the
26:13hole. So, essentially, there are
26:15multiple levels of challenges in getting
26:17P-type gallium oxide going. And so, so
26:19there's a motivation to now integrate
26:21other oxides uh P-type oxides with with
26:25gallium oxide. So, I'll give you a like
26:27brief highlight of some of these efforts
26:28and then towards end of the talk, I will
26:30I will highlight some recent results on
26:32transistors using this material.
26:36Okay, so the the simplest topology would
26:38be to just put a field plate in. So, so
26:40if you have a metal semiconductor
26:42junction, we're going to have electric
26:44field crowding at the edges of the this
26:47metal over here.
26:49And the The way to to deal with this
26:52issue is to add a dielectric and a field
26:55plate metal and we can spread out the
26:57electric field and you still have two
26:59edges
27:00>> [snorts]
27:00>> where where the electric field is the
27:03maximum, right? We're going to spread
27:04out this field into these two peaks over
27:07here.
27:08So now
27:10this works quite well in in in most of
27:13my characters. So to further push this
27:16we've been exploring using high
27:18permittivity dielectrics. So basically
27:20we can add
27:22dielectrics which have which
27:24which which have a much higher
27:25dielectric constant and what this lets
27:28us do is it further helps us in
27:30spreading out the depletion region and
27:33the electric field can be lowered
27:36by using a high permittivity dielectric
27:38instead of a low permittivity dielectric
27:39for the field plate oxide.
27:41So so we experimented with this idea way
27:43back in 2021 with Epi from Keima from
27:48Jacob Leach. These are thin like 1.7
27:51micron
27:52relatively heavily doped
27:54epitaxial layers and we
27:57added these high dielectric constant
27:59field plates.
28:01In this particular case it was a
28:02superlattice of barium titanate and
28:04strontium titanate that got annealed and
28:06mixed up and with an effective
28:08dielectric constant close to 300. And by
28:11doing this we were able to get 600
28:16close to 700 V breakdown
28:18in this thin epitaxial layer
28:21without compromising the on state of the
28:23device, right? So the no field plate
28:25device and the field plate device have
28:26the exact same on state characteristics
28:29in terms of on resistance, the turn on
28:32voltage and so on.
28:33But we got a huge improvement in in the
28:36reverse blocking capability which is
28:37exactly what we want and so we were able
28:39to get
28:40on resistance which are below 1 mΩ cm
28:43squared at 600 V
28:44using this approach.
28:46Later we extended this idea by using a
28:49load of thicker epitaxial layers, 11
28:51microns of a protection layer and with
28:53low doping.
28:54Uh and you can look at these log ID
28:56curves. These are very ideal diodes, uh
28:59Schottky diodes essentially, ideality
29:01close to one,
29:02uh nicely scaling with area, and uh the
29:05breakdown voltage was also
29:08constant across 50 [snorts] micron
29:10diameters to 300 micron diameters in
29:12this in this uh in this particular um
29:15uh device, and we were now able to get
29:17up to like 2.2 kV uh Schottky diodes
29:22uh
29:22on uh gallium oxide layers with a high K
29:25field plate.
29:29So so So these devices still have a
29:32triangular electric field profile uh
29:34because you have when you deplete the
29:35charge, you have uniform charge uh and
29:38and you use Poisson's equation or
29:41Gauss's law. So basically, you will find
29:43the electric field is is is linear, uh
29:45you have triangular field profile.
29:48But in silicon, you can actually do
29:50charge balancing. So essentially, you
29:52can have columns of P-type and N-type
29:54material
29:55uh which if the quan- if the charge is
29:58equal, then you can get a net zero
30:00charge in the in the depleted layer,
30:03uh which results in a flat or a constant
30:06electric field profile, and that gives
30:08you twice the breakdown voltage. So
30:10that's the concept of a silicon
30:11superjunction.
30:13Um
30:14So you get twice the breakdown voltage,
30:16but more importantly, the fact that you
30:18actually have these alternating pillars
30:20of P and N-type region
30:22uh means uh that you can actually now
30:24dope the material heavily and still
30:25deplete it. And so that actually gives
30:28you a much lower on resistance. So the
30:29winner in a superjunction is not just
30:31twice the
30:32uh breakdown twice the voltage, but
30:34actually a much reduced on resistance
30:36because now you're able to dope the
30:37material higher and still deplete it
30:39using these columns of charge balanced
30:41P-type and N-type materials. So, to do
30:43something similar in gallium oxide, uh
30:45it's it's going to be hard because we
30:46don't have P-type material, right? So,
30:48we were now thinking about ideas of
30:49using a dielectric and a fringing
30:51electric field within the dielectric to
30:54be able to now have a similar effect,
30:56superjunction-like effect in gallium
30:58oxide. And we tested out this idea uh in
31:01a in a lateral geometry first. Uh we
31:03made some analytical models of this
31:05design and you can effectively mimic a
31:07superjunction by carefully choosing the
31:10the aspect ratio of the structure,
31:13uh the width of these dielectrics, uh
31:16and the aspect ratio. If if you
31:17carefully choose those values, then
31:19experimentally we've been able to show
31:21that you can actually get very high
31:22figure of merit, uh which at this point
31:25in 2022 crossed the silicon carbide line
31:28uh with just 5 microns of um
31:31anode-to-cathode distance in a lateral
31:33topology, uh we were able to block close
31:35to 1,500 V
31:37on average electric field of 3 MV/cm.
31:40Uh so,
31:41so so one could kind of so so a new
31:44material with a new challenge in terms
31:46of not having P-type leads to uh you
31:48know, you have to come up with new ideas
31:51in terms of field management. And so so
31:53using dielectrics carefully can can
31:55uh can kind of uh enable such such novel
31:58devices.
32:00So, uh the other way to engineer the
32:02electric field profile would be to go
32:05uh take advantage of the geometry,
32:07right? So, in this case, a planar
32:09Schottky is going to have um
32:11triangular field profile, but if we etch
32:14down this layer, add a dielectric, and
32:17have a sidewall metal, then we can have
32:20field cancellation,
32:22and we can reduce the electric field at
32:24this metal-semiconductor
32:26uh
32:27junction.
32:28And we can push the peak electric field
32:31from the metal-semiconductor junction
32:33into the into the um
32:36into the semiconductor layer.
32:38Uh and so if you get able to push the
32:40electric field into the semiconductor
32:42layer, then that basically means that
32:44uh, field emission tunneling under
32:46reverse bias is reduced. So, this is the
32:49reduced surface field effect or resurf
32:51effect. And so, so in my group um, we
32:54basically took this idea and then
32:56modified it to include high K
32:58dielectrics.
32:59And if we had high K dielectrics, we can
33:01actually further reduce the surface
33:04electric field
33:06uh, compared to a low K dielectric. And
33:08what that helps us is that now we can
33:11start using a low work function metal
33:14and you can make a Schottky diode with a
33:16low turn on voltage while still
33:18preserving the reverse leakage because
33:20you're reducing the surface electric
33:22field. So, it kind of removes the
33:23trade-off or modifies the trade-off
33:24>> [snorts]
33:25>> between the on state and off state uh,
33:27for a Schottky diode.
33:29So, we further uh, simulated these
33:31devices and uh, you can if you if you
33:34engineer them uh, carefully with the
33:36right aspect ratio, you can get to very
33:38low surface electric fields in these
33:40devices. Okay?
33:41And and um,
33:43and you can push the peak electric field
33:45within the semiconductor. And and so,
33:48so, so, so this was kind of
33:50experimentally realized um,
33:52using platinum and ruthenium as uh, the
33:55metal
33:57uh, metal layer uh, and barium titanate
34:00as the high K uh, oxide.
34:03And we were able to demonstrate um,
34:06tunability of the forward turn on
34:08voltage. So, lower uh, work function
34:10metal uh, like ruthenium gave gave us a
34:13lower turn on voltage as still good
34:15current densities uh, and uh, platinum
34:18gave us slightly higher uh, turn on
34:19voltage. And we also made large area
34:21diodes. These are 2 by 2 mm diodes that
34:24are
34:24relevant uh, for power electronics. So,
34:27essentially here we were able to measure
34:29on wafer uh, currents up to 20 amperes
34:32uh, in a 2 by 2 mm uh, device using
34:35ruthenium as a contact.
34:39And what is outstanding is that the
34:41reverse leakage in these devices are
34:43close to noise floor and very low
34:45values.
34:47And when we scale the area of these
34:49devices, the breakdown voltage does
34:50suffer, which means we do have some weak
34:52spots when we scale the area. We still
34:54need to understand the microstructure
34:56and the leakage mechanisms.
34:59And and maybe killer defects in the
35:01epitaxial layers and so on. So these are
35:03open questions that is
35:05these are
35:06important questions to look at
35:08when we try to scale the area of the
35:10devices. But nevertheless, we can see
35:12that the reverse leakage current in
35:13these structures are extremely extremely
35:15low.
35:18And and what is now more exciting is we
35:19did some capacitance measurements,
35:21estimated the stored charge in these in
35:24these diodes and try to compare it to
35:27silicon carbide bare die
35:30off-the-shelf components. And we are
35:32able to get lower
35:34charge, lower stored energy in these in
35:36these in these diodes compared to
35:39silicon carbide. So we actually have the
35:41lowest
35:42stored charge forward voltage product of
35:44any gallium oxide diode
35:46with more than a 1 kV 1 amp rating in
35:49these in these
35:51in this trench high K recess
35:54diode approach.
35:58So so so more more recently we have
36:01uh
36:03started working on adding these
36:06P-type oxides. So we've done nickel
36:08oxide in this slide I'm showing chromium
36:10oxide.
36:11So this is thin layers of P-like oxides
36:15which give you a built-in potential
36:17close to 2 volts.
36:19So compared to a Schottky, you do suffer
36:21slightly higher forward voltage drop,
36:24but the enhanced built-in potential here
36:27gives you outstanding reverse leakage
36:28characteristics, almost noise floor
36:30level leakage. And we've been able to
36:31make diodes with a few amps forward
36:35current and breakdown voltages as high
36:37as 3 kV.
36:39Uh and so so once we made these uh
36:43amp
36:443 kV 1 amp 3 kV diodes, we collaborated
36:47uh with uh The Ohio State University,
36:49Professor Jin Wang's group, to do double
36:52pulse measurements in these in these
36:54diodes. Uh so and then estimated or
36:57calculated the reverse recovery time in
36:59these diodes, which is presented in uh
37:01APEC and uh
37:03uh the Applied Power Electronics
37:04Conference uh a few months ago. And so
37:07here uh we can get extremely impressive
37:11reverse recovery times uh in these
37:13diodes. So although we are adding a
37:15P-type oxide that transport is dominated
37:17by electrons, so so the the reverse
37:20recovery is still very fast, unlike, you
37:22know, uh silicon PIN diode where you
37:25worry about conductivity modulation uh
37:27and reverse recovery is much large uh a
37:29larger time. So so so this reverse
37:32recovery time starts to look more like a
37:33Schottky diode, although we have uh you
37:35know, P-type oxide over here. So
37:37transport is dominated by electrons in
37:39our understanding, cuz these things need
37:41to be studied more carefully.
37:43Uh so so so now, you know, these uh
37:46diodes these are some of the highest
37:49test voltage and lowest reverse recovery
37:51charge reported for gallium oxide. And
37:53and these numbers are uh promising. We
37:56did some benchmarking with silicon
37:57carbide and the reverse recovery time uh
38:00is definitely uh
38:02smaller than silicon carbide at at
38:04similar voltage rating.
38:06So that's quite exciting and you know,
38:07we continue to push some of this very
38:09recent results.
38:11And um
38:12and more recently in my group, we've
38:14been able to push um these
38:17heterojunction diodes uh to about 10
38:20kilovolt uh with reasonable on
38:22resistance translating to a figure of
38:24merit that's very close to silicon
38:26carbide theoretical line.
38:28And this is
38:30diode that survived three sweeps
38:33and even more like 10 kilovolts and this
38:36[snorts] is basically the
38:37characteristics before and after the
38:38sweep.
38:39And if you translate
38:41this is 20 micron thick AP and if you
38:43translate this to an electric field at
38:46the junction it works out to be
38:48something around 5 mega or 5.3 mega per
38:51centimeter.
38:52So this is very recent results
38:54to be presented in the device research
38:56conference
38:57in Michigan later later this month by
39:00Ejan and Liu.
39:02So we are starting to see these 10 KB
39:04diodes and there there there there is
39:05also reports from University of Florida.
39:08So they've been able to measure up to
39:1013.5 KB in gallium oxide as well. So
39:13and there's lots of papers from China
39:15where they're starting to report high
39:17breakdown voltages as well. So so it's
39:19quite quite an exciting time for the for
39:21the material.
39:22So so that's the diode. So so so
39:24constant progress in terms of
39:26high voltage
39:28low stored charge diodes.
39:31So in my group in the remaining
39:345 or 10 minutes I would like to
39:35highlight some work we are doing on the
39:37transistors or switches.
39:39So
39:40So there is no P type availability right
39:43and so we have to do a junctionless
39:46architecture. In this case
39:49these are vertical finfets so we define
39:51narrow channels about 200 nanometer
39:55wide channels of low doped gallium oxide
39:59and then we use metal oxide
40:01semiconductor junction on the side wall
40:03of this fin
40:04for the gating purpose. And so so then
40:07that way you gate through the side walls
40:09both the side walls and then you control
40:11the current flow from the source to the
40:13bottom [snorts] drain. Right. So it's a
40:15vertical finfet no junctions, no P-type
40:18layers involved, all unipolar.
40:21So, hopefully these can be like fast
40:22switching
40:24um
40:24transistors in the future.
40:26So, this is the SEM image of the fin fin
40:30SEM image of the transistors we have
40:31made. You can see
40:34near vertical fins, nice corner rounding
40:37to manage electric fields in these
40:38devices.
40:39Uh and we can see nice gates on the
40:42sidewall of these devices. The
40:43fabrication is a little bit challenging,
40:46nevertheless we've been able to
40:47fine-tune this process over
40:49over generations and now we have a nice
40:52a working process in here in the UCSB
40:54nanofab, which is a fantastic nanofab
40:57for for research.
41:00Uh
41:01And so, so so so these are the vertical
41:03finfets and and earlier this year sort
41:06of
41:07right so so so so my group so we
41:10reported 1.8 kV transistors.
41:15Uh so so these are 1.8 kV transistors um
41:19with 3.2 mΩ cm² on resistance.
41:22Uh and the novelty here is that we added
41:25a field oxide in the bottom of the
41:27trench. When you add a field oxide,
41:29uh this can result in enhanced breakdown
41:32voltage as seen from this particular
41:33comparison. So, without the field oxide,
41:37these devices broke down at 800 V, but
41:39we were able to push it out to 1.8 kV
41:42um
41:43by addition of the field
41:45So so since we're working on bulk
41:47substrates,
41:49uh these devices actually have excellent
41:51on-off ratio. The off-state leakage
41:53current is
41:55uh pretty low. The on-off ratio is very
41:57good, 10 to the 9.
41:58Um
42:00And so so that's because we have the
42:02benefit of working on a very
42:03high-quality crystal crystalline
42:04substrate
42:06uh that nicely follows onto the
42:07epitaxial layer in terms of the quality.
42:11Um
42:12And
42:13so even more recently, which is this is
42:16some very new data, it will be presented
42:18later this month
42:20later this month at the device research
42:22conference. Again, Saurabh went on to
42:24become a professor at NC State.
42:26So Saurabh is going to present this in
42:28DRC
42:29end of this month. She's been able to
42:31make 3.4 kilovolt transistors.
42:35Um again, excellent on-off ratio 10 to
42:37the 10. These are enhancement mode. Um
42:40slightly higher on resistance in this
42:42case and we know how to how to make this
42:43better in the future generations.
42:45And we are able to get breakdown very
42:49low reverse leakage for the transistor
42:51until it catastrophically breaks down at
42:543.4 kilovolt here. So the most exciting
42:58part about this particular,
42:59you know, device and this generation of
43:02device is actually when we compare this
43:04to gallium nitride and silicon carbide.
43:07So so although gallium nitride and
43:09silicon carbide can genetically hold
43:10high electric fields,
43:12but uh
43:14but for for devices,
43:17say a 3.3 kV devices, devices in silicon
43:20carbide, you actually need 33 microns of
43:22drift layer. Uh and
43:25and so this translates to an average
43:27electric field handling capability of
43:29about 1 megavolt per centimeter. And
43:31that's the same for gallium nitride as
43:33gallium nitride FinFETs from MIT.
43:36Uh and so
43:37um
43:38whereas in gallium oxide, we are able to
43:40block 3.4 kV with just 11 microns of the
43:44drift layer. And this translates to
43:45about three times higher electric field
43:47handling capability in this material
43:49compared to gallium nitride and silicon
43:50carbide. So I plotted this average
43:53electric field as a function of the
43:54actual breakdown voltage. So normally
43:56lots of groups report excellent high
43:59average fields at low
44:02uh gate drain distance in a lateral
44:03device or a low thickness epi in a
44:05vertical device.
44:07But but scaling that to higher voltages
44:09is actually challenging. But here we've
44:11been able to
44:12simultaneously get high breakdown fields
44:16at high breakdown voltages. And these
44:19are some record results right now. We
44:21presented later this month in DRC.
44:25I would also like to give a shout out to
44:28an excellent result from Japan.
44:30This is 10 kV transistor from Novel
44:32Crystal Technology. And uh and
44:36And so this is an amazing
44:39development for the field. So so this is
44:41a very recent work from Japan. They
44:43demonstrated 10 kV vertical transistors
44:45in gallium oxide as well.
44:47Okay, with that I'd like to summarize
44:49that you know
44:50using this low doped epitaxial layers,
44:55we've been able to get the highest
44:56average field in any vertical power
44:58transistor.
45:00And more recently also some diodes
45:02impressive diodes. And we're starting to
45:04switch these devices. And And the diodes
45:06are showing some early promise in terms
45:08of the reverse recovery time and so on
45:12and so forth. And again a big shout out
45:14to my entire group here
45:15and funding agencies and collaborators.
45:19So with that I would like to
45:22thank everyone for your attention and
45:24I'll be very happy to answer questions.
45:27>> Thank you, Sriram.
45:28Great presentation and a lot of results.
45:30An incredibly lot of results and even
45:32this year.
45:33>> Yeah.

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